The interrupt status register R_IS is the standard clear-on-write behaviour.
This was unimplemented and defaulting to updating the register to the written
value. Implemented clear-on-write.
Reported-by: Jason Wu <hua...@xilinx.com>
Signed-off-by: Peter Crosthwaite <peter.crosthwa...@xilinx.com>
---
hw/xilinx_axienet.c | 4 ++++
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/hw/xilinx_axienet.c b/hw/xilinx_axienet.c
index baae02b..f2e3bf1 100644
--- a/hw/xilinx_axienet.c
+++ b/hw/xilinx_axienet.c
@@ -591,6 +591,10 @@ static void enet_write(void *opaque, hwaddr addr,
s->maddr[s->fmi & 3][addr & 1] = value;
break;
+ case R_IS:
+ s->regs[addr] &= ~value;
+ break;
+
case 0x8000 ... 0x83ff:
s->ext_mtable[addr - 0x8000] = value;
break;
--
1.7.0.4
