Re: [Qemu-devel] [PATCH v1 15/28] riscv: plic: Always set sip.SEIP bit for HS

On Fri, 23 Aug 2019 16:38:29 PDT (-0700), Alistair Francis wrote: When the PLIC generates an interrupt ensure we always set it for the SIP CSR that corresponds to the HS (V=0) register. Signed-off-by: Alistair Francis --- hw/riscv/sifive_plic.c | 12 +++- 1 file changed, 11 insertions(

[Qemu-devel] [PATCH v1 15/28] riscv: plic: Always set sip.SEIP bit for HS

When the PLIC generates an interrupt ensure we always set it for the SIP CSR that corresponds to the HS (V=0) register. Signed-off-by: Alistair Francis --- hw/riscv/sifive_plic.c | 12 +++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/si