On Tue, Jan 21, 2020 at 11:05 PM Jonathan Behrens wrote:
>
> I was just doubling checking the status of this patch because it conflicts
> with the "RISC-V TIME CSR for privileged mode" PR that was just sent out, and
> it seems this never got merged? In any case, perhaps these changes should be
I was just doubling checking the status of this patch because it conflicts
with the "RISC-V TIME CSR for privileged mode" PR that was just sent out,
and it seems this never got merged? In any case, perhaps these changes
should be rolled into that patch?
On Wed, Aug 21, 2019 at 1:37 PM Palmer
On Wed, 14 Aug 2019 20:19:39 PDT (-0700), jonat...@fintelia.io wrote:
Ping! What is the status of this patch?
Sorry, I must have lost track of it. I've added it to my patch queue.
On Wed, Jul 3, 2019 at 2:02 PM Jonathan Behrens
wrote:
Bin, that proposal proved to be somewhat more
Ping! What is the status of this patch?
On Wed, Jul 3, 2019 at 2:02 PM Jonathan Behrens
wrote:
> Bin, that proposal proved to be somewhat more controversial than I was
> expecting, since it was different than how currently available hardware
> worked. This option seemed much more likely to be
Bin, that proposal proved to be somewhat more controversial than I was
expecting, since it was different than how currently available hardware
worked. This option seemed much more likely to be accepted in the short
term.
Jonathan
On Mon, Jul 1, 2019 at 9:26 PM Bin Meng wrote:
> On Tue, Jul 2,
On Tue, Jul 2, 2019 at 8:20 AM Alistair Francis wrote:
>
> On Mon, Jul 1, 2019 at 8:56 AM wrote:
> >
> > From: Jonathan Behrens
> >
> > QEMU currently always triggers an illegal instruction exception when
> > code attempts to read the time CSR. This is valid behavor, but only if
> > the TM bit
On Mon, Jul 1, 2019 at 8:56 AM wrote:
>
> From: Jonathan Behrens
>
> QEMU currently always triggers an illegal instruction exception when
> code attempts to read the time CSR. This is valid behavor, but only if
> the TM bit in mcounteren is hardwired to zero. This change also
> corrects
From: Jonathan Behrens
QEMU currently always triggers an illegal instruction exception when
code attempts to read the time CSR. This is valid behavor, but only if
the TM bit in mcounteren is hardwired to zero. This change also
corrects mcounteren and scounteren CSRs to be 32-bits on both 32-bit
