David Gibson wrote on 05/13/2017 02:59:16
AM:
> From: David Gibson
> On Fri, May 12, 2017 at 09:34:33AM -0500, alar...@ddci.com wrote:
> > David Gibson wrote on 05/12/2017
01:52:04
Sorry for the long delay getting back to you. I was out of town for a
while.
> > > > +}
> > > > +uin
On Fri, May 12, 2017 at 09:34:33AM -0500, alar...@ddci.com wrote:
> David Gibson wrote on 05/12/2017 01:52:04
> AM:
>
> > From: David Gibson
> > To: Aaron Larson
> > Cc: ag...@suse.de, qemu-devel@nongnu.org, qemu-...@nongnu.org
> > Date: 05/12/2017 01:52 AM
> > Subject: Re: [PATCH v2] target-p
David Gibson wrote on 05/12/2017 01:52:04
AM:
> From: David Gibson
> To: Aaron Larson
> Cc: ag...@suse.de, qemu-devel@nongnu.org, qemu-...@nongnu.org
> Date: 05/12/2017 01:52 AM
> Subject: Re: [PATCH v2] target-ppc: Enable open-pic timers to count and
generate interrupts
>
> On Tue, May 02,
On Tue, May 02, 2017 at 07:57:22PM -0700, Aaron Larson wrote:
>
> Previous QEMU open-pic implemented the 4 open-pic timers including all
> timer registers, but the timers did not "count" or generate any
> interrupts. The patch makes the timers both count and generate
> interrupts. The timer cloc
Previous QEMU open-pic implemented the 4 open-pic timers including all
timer registers, but the timers did not "count" or generate any
interrupts. The patch makes the timers both count and generate
interrupts. The timer clock frequency is fixed at 100MHZ.
Signed-off-by: Aaron Larson
---
hw/in
