This is the second set of patches for A64 Neon. The last patch
set did a complete coverage of some of the smaller and simpler
instruction groupings; this patch set attacks a few of the
larger groupings (3-same; scalar 3-same; 3-different; shift-imm;
scalar shift-imm) and doesn't attempt complete coverage of them.
My rule of thumb was to (a) implement enough instructions to
demonstrate that the general decode and set of sub-functions/loops
was adequate (b) aim to cover at least as much as the SuSE tree.
Remaining things in SuSE 1.6 tree not yet implemented:
3-reg-same MLA, MLS, MUL, PMUL, SMAX, UMAX, SMIN, UMIN,
SSHL, USHL, SQSHL, UQSHL, SRSHL, URSHL
2-reg-misc XTN, FABS, FNEG, NOT
Changes v1->v2:
* added _i32 versions of read_vec_element and write_vec_element,
which let us avoid messing about with TCGv_i64 temporaries and
truncation when we're operating on 32 bits at a time and calling
helpers which take and return TCGv_i32 values
(these are in patch 1 for read and patch 6 for write)
* patch 3: use -(setcond(cond)) for CMGT and friends rather than
setcond(!cond) - 1
* patch 5: use tcg_andc, tcg_orc in 3same-logic
* patch 6: add missing unsupported_encoding() call in disas_simd_3same_int
(some unsupported insns were asserting)
* patch 6: simd_3same_int: fix table naming, make them static const,
move the typedef to top of file so it can be used by other fns
* patch 8: use deposit in shift-by-immediate
RTH: I've applied your reviewed-by tag to most of these patches
since they're either the same or (for patches 3, 5, 8) just the
minor tweaks you recommended. I've left patches 1 and 6 without
your tag, because of (a) the read/write_vec_element_i32() addition
and (b) patch 6 got more fixes than the others.
thanks
-- PMM
Alex Bennée (1):
target-arm: A64: Add SIMD shift by immediate
Peter Maydell (7):
target-arm: A64: Add SIMD three-different multiply accumulate insns
target-arm: A64: Add SIMD three-different ABDL instructions
target-arm: A64: Add SIMD scalar 3 same add, sub and compare ops
target-arm: A64: Add top level decode for SIMD 3-same group
target-arm: A64: Add logic ops from SIMD 3 same group
target-arm: A64: Add integer ops from SIMD 3-same group
target-arm: A64: Add simple SIMD 3-same floating point ops
target-arm/translate-a64.c | 1281 +++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 1253 insertions(+), 28 deletions(-)
--
1.8.5
