Re: [Qemu-devel] [PATCH v2 00/19] Add support for multiple address spaces per CPU and use it for ARM TrustZone

On Mon, Jan 11, 2016 at 01:04:29PM +, Peter Maydell wrote: > Ping again (though I know Paolo said on IRC he'd put this on > his list to look at). I have a rebased branch at > https://git.linaro.org/people/peter.maydell/qemu-arm.git multi-ases-2 > but the only differences are some minor fixes

Re: [Qemu-devel] [PATCH v2 00/19] Add support for multiple address spaces per CPU and use it for ARM TrustZone

Ping again (though I know Paolo said on IRC he'd put this on his list to look at). I have a rebased branch at https://git.linaro.org/people/peter.maydell/qemu-arm.git multi-ases-2 but the only differences are some minor fixes to conflicts in the virt board patches following the GPIO device going

Re: [Qemu-devel] [PATCH v2 00/19] Add support for multiple address spaces per CPU and use it for ARM TrustZone

Ping for a review request now we're pretty nearly done with 2.5 ? thanks -- PMM On 16 November 2015 at 14:05, Peter Maydell wrote: > This patch series adds support to QEMU's core exec/memory code for > CPUs which have more than one address space, and uses it for > ARM

[Qemu-devel] [PATCH v2 00/19] Add support for multiple address spaces per CPU and use it for ARM TrustZone

This patch series adds support to QEMU's core exec/memory code for CPUs which have more than one address space, and uses it for ARM TrustZone. In particular, a TZ CPU will have two physical address spaces (Secure and Non-secure), and the patchset allows a board model to create these both