Re: [Qemu-devel] [PATCH v2 07/17] RISC-V: add vector extension atomic instructions

On 9/11/19 2:25 AM, liuzhiwei wrote: > +case 64: > +if (vector_elem_mask(env, vm, width, lmul, i)) { > +int64_t tmp; > +idx= (target_long)env->vfp.vreg[src2].s64[j]; > +addr = idx + env->gpr[rs1]; > + > +#

[Qemu-devel] [PATCH v2 07/17] RISC-V: add vector extension atomic instructions

From: LIU Zhiwei Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 18 + target/riscv/insn32.decode | 21 + target/riscv/insn_trans/trans_rvv.inc.c | 36 + target/riscv/vector_helper.c| 1467 +++ 4 files changed, 1