[Qemu-devel] [PATCH v2 17/32] arm/translate-a64: initial decode for simd_two_reg_misc_fp16

2018-02-08 Thread Alex Bennée
This actually covers two different sections of the encoding table: Advanced SIMD scalar two-register miscellaneous FP16 Advanced SIMD two-register miscellaneous (FP16) The difference between the two is covered by a combination of Q (bit 30) and S (bit 28). Notably the FRINTx instructions ar

Re: [Qemu-devel] [PATCH v2 17/32] arm/translate-a64: initial decode for simd_two_reg_misc_fp16

2018-02-08 Thread Richard Henderson
On 02/08/2018 09:31 AM, Alex Bennée wrote: > @@ -11472,6 +11512,8 @@ static void disas_data_proc_simd(DisasContext *s, > uint32_t insn) > if (fn) { > fn(s, insn); > } else { > +/* fprintf(stderr, "%s: failed to find %#4x @ %#" PRIx64 "\n", */ > +/* __func