Re: [Qemu-devel] [PATCH v2 19/35] target-arm: A64: Make cache ID registers visible to AArch64

2014-02-11 Thread Hu Tao
On Fri, Feb 07, 2014 at 10:27:35AM +, Peter Maydell wrote: > On 7 February 2014 07:35, Hu Tao wrote: > > On Fri, Jan 31, 2014 at 03:45:27PM +, Peter Maydell wrote: > >> Make the cache ID system registers (CLIDR, CCSELR, CCSIDR, CTR) > > > > s/CCSELR/CSSELR/ > > > >> visible to AArch64. The

Re: [Qemu-devel] [PATCH v2 19/35] target-arm: A64: Make cache ID registers visible to AArch64

2014-02-09 Thread Peter Crosthwaite
On Sun, Feb 9, 2014 at 9:52 PM, Peter Maydell wrote: > On 9 February 2014 02:15, Peter Crosthwaite > wrote: >> On Sat, Feb 1, 2014 at 1:45 AM, Peter Maydell >> wrote: >>> -{ .name = "CCSIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0, >>> +{ .name = "CCSIDR", .state = ARM_CP_ST

Re: [Qemu-devel] [PATCH v2 19/35] target-arm: A64: Make cache ID registers visible to AArch64

2014-02-09 Thread Peter Maydell
On 9 February 2014 02:15, Peter Crosthwaite wrote: > On Sat, Feb 1, 2014 at 1:45 AM, Peter Maydell > wrote: >> -{ .name = "CCSIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0, >> +{ .name = "CCSIDR", .state = ARM_CP_STATE_BOTH, >> + .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1,

Re: [Qemu-devel] [PATCH v2 19/35] target-arm: A64: Make cache ID registers visible to AArch64

2014-02-08 Thread Peter Crosthwaite
On Sat, Feb 1, 2014 at 1:45 AM, Peter Maydell wrote: > Make the cache ID system registers (CLIDR, CCSELR, CCSIDR, CTR) > visible to AArch64. These are mostly simple 64-bit extensions of the > existing 32 bit system registers and so can share reginfo definitions. > CTR needs to have a split definit

Re: [Qemu-devel] [PATCH v2 19/35] target-arm: A64: Make cache ID registers visible to AArch64

2014-02-07 Thread Peter Maydell
On 7 February 2014 07:35, Hu Tao wrote: > On Fri, Jan 31, 2014 at 03:45:27PM +, Peter Maydell wrote: >> Make the cache ID system registers (CLIDR, CCSELR, CCSIDR, CTR) > > s/CCSELR/CSSELR/ > >> visible to AArch64. These are mostly simple 64-bit extensions of the >> existing 32 bit system regis

Re: [Qemu-devel] [PATCH v2 19/35] target-arm: A64: Make cache ID registers visible to AArch64

2014-02-06 Thread Hu Tao
On Fri, Jan 31, 2014 at 03:45:27PM +, Peter Maydell wrote: > Make the cache ID system registers (CLIDR, CCSELR, CCSIDR, CTR) s/CCSELR/CSSELR/ > visible to AArch64. These are mostly simple 64-bit extensions of the > existing 32 bit system registers and so can share reginfo definitions. Accord

[Qemu-devel] [PATCH v2 19/35] target-arm: A64: Make cache ID registers visible to AArch64

2014-01-31 Thread Peter Maydell
Make the cache ID system registers (CLIDR, CCSELR, CCSIDR, CTR) visible to AArch64. These are mostly simple 64-bit extensions of the existing 32 bit system registers and so can share reginfo definitions. CTR needs to have a split definition, but we can clean up the temporary user-mode implementatio