On 05/12/2015 02:54 AM, Peter Maydell wrote:
> Ideally it would be nice to have support in TCG so that a frontend
> could output a TCG load/store op with a flag for "unaligned access
> OK" or not. ARM also has this issue of some load/stores wanting to
> do alignment traps and some not.
Yes, that w
On 11 May 2015 at 14:15, Yongbok Kim wrote:
> The thing is that the fact misaligned accesses of MSA LD/ST should be allowed
> in R5 cores
> while all other instructions are not allowed.
> Therefore it is required which types of instruction is triggering the
> misaligned accesses.
>
> Initially I
On 11/05/2015 12:30, Yongbok Kim wrote:
> @@ -391,6 +391,37 @@ hwaddr cpu_mips_translate_address(CPUMIPSState *env,
> target_ulong address, int r
> }
> }
>
> +bool cpu_mips_validate_msa_block_access(CPUMIPSState *env, target_ulong addr,
> +int rw, in
Hi Yongbok,
On 11/05/2015 14:15, Yongbok Kim wrote:
> Hi
> I have implemented this to have a flag which isn't that nice.
>
> The thing is that the fact misaligned accesses of MSA LD/ST should be allowed
> in R5 cores
> while all other instructions are not allowed.
> Therefore it is required whic
On 11/05/2015 12:30, Yongbok Kim wrote:
> MIPS SIMD Architecture vector loads and stores require misalignment support.
> MSA Memory access should work as an atomic operation. Therefore, it has to
> check validity of all addresses for an access if it is spanning into two
> pages.
>
> Introduced mis
Am 11.05.2015 um 13:30 schrieb Yongbok Kim:
> MIPS SIMD Architecture vector loads and stores require misalignment support.
> MSA Memory access should work as an atomic operation. Therefore, it has to
> check validity of all addresses for an access if it is spanning into two
> pages.
>
> Introduce
MIPS SIMD Architecture vector loads and stores require misalignment support.
MSA Memory access should work as an atomic operation. Therefore, it has to
check validity of all addresses for an access if it is spanning into two pages.
Introduced misaligned flag to indicate MSA ld/st is ongoing, is us
