On 30 October 2015 at 21:32, Peter Crosthwaite
wrote:
> On Fri, Oct 30, 2015 at 2:10 PM, Peter Maydell
> wrote:
>> This still confuses me. What I was expecting to see was something like:
>>
>> /* Monitor mode vector table; entry points which will only be reached
>> * if the guest kernel
On Fri, Oct 30, 2015 at 2:10 PM, Peter Maydell wrote:
> On 30 October 2015 at 05:35, Peter Crosthwaite
> wrote:
>> Firstly, enable monitor mode and PSCI, both are which are features of
>> this board.
>>
>> In addition to PSCI, this board also uses SMC for cache maintainence
>> ops. This means we
On 30 October 2015 at 05:35, Peter Crosthwaite
wrote:
> Firstly, enable monitor mode and PSCI, both are which are features of
> this board.
>
> In addition to PSCI, this board also uses SMC for cache maintainence
> ops. This means we need a secure monitor to catch these and nop them.
> Use the ARM
Firstly, enable monitor mode and PSCI, both are which are features of
this board.
In addition to PSCI, this board also uses SMC for cache maintainence
ops. This means we need a secure monitor to catch these and nop them.
Use the ARM boot board-setup feature to implement this. All traps to
monitor
