Revisit the definitions of the cp registers TTBR0/1 and TTBRC in such a way to
use the AArch32 ids format when the guest is using a 32bit model.
Signed-off-by: Alvise Rigo <a.r...@virtualopensystems.com>
---
target-arm/helper.c | 38 +++++++++++++++++++++++++++-----------
1 file changed, 27 insertions(+), 11 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 30973cc..daa707e 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1390,6 +1390,16 @@ static void vmsa_ttbcr_raw_write(CPUARMState *env, const
ARMCPRegInfo *ri,
env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> maskshift);
}
+static void vmsa_control_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+ if (ri->state == ARM_CP_STATE_AA64) {
+ raw_write(env, ri, value);
+ } else {
+ vmsa_ttbcr_raw_write(env, ri, value);
+ }
+}
+
static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
@@ -1417,6 +1427,16 @@ static void vmsa_tcr_el1_write(CPUARMState *env, const
ARMCPRegInfo *ri,
env->cp15.c2_control = value;
}
+static void vmsa_control_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+ if (ri->state == ARM_CP_STATE_AA64) {
+ vmsa_tcr_el1_write(env, ri, value);
+ } else {
+ vmsa_ttbcr_write(env, ri, value);
+ }
+}
+
static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
@@ -1439,20 +1459,16 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
{ .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el1),
- .writefn = vmsa_ttbr_write, .resetvalue = 0 },
+ .writefn = vmsa_ttbr_write, .resetvalue = 0, .type = ARM_CP_NO_MIGRATE,
},
{ .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el1),
- .writefn = vmsa_ttbr_write, .resetvalue = 0 },
- { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64,
+ .writefn = vmsa_ttbr_write, .resetvalue = 0, .type = ARM_CP_NO_MIGRATE,
},
+ { .name = "TCR_EL1", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
- .access = PL1_RW, .writefn = vmsa_tcr_el1_write,
- .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
+ .access = PL1_RW, .writefn = vmsa_control_write,
+ .resetfn = vmsa_ttbcr_reset, .raw_writefn = vmsa_control_raw_write,
.fieldoffset = offsetof(CPUARMState, cp15.c2_control) },
- { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
- .access = PL1_RW, .type = ARM_CP_NO_MIGRATE, .writefn = vmsa_ttbcr_write,
- .resetfn = arm_cp_reset_ignore, .raw_writefn = vmsa_ttbcr_raw_write,
- .fieldoffset = offsetoflow32(CPUARMState, cp15.c2_control) },
{ .name = "DFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_data),
.resetvalue = 0, },
@@ -1683,11 +1699,11 @@ static const ARMCPRegInfo lpae_cp_reginfo[] = {
.access = PL1_RW, .type = ARM_CP_64BIT,
.readfn = par64_read, .writefn = par64_write, .resetfn = par64_reset },
{ .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0,
- .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE,
+ .access = PL1_RW, .type = ARM_CP_64BIT,
.fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el1),
.writefn = vmsa_ttbr_write, .resetfn = arm_cp_reset_ignore },
{ .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1,
- .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE,
+ .access = PL1_RW, .type = ARM_CP_64BIT,
.fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el1),
.writefn = vmsa_ttbr_write, .resetfn = arm_cp_reset_ignore },
REGINFO_SENTINEL
--
1.8.3.2
