Re: [Qemu-devel] [PATCH v2 7/9] i.MX: Add i.MX6 SOC implementation.

Le 01/03/2016 17:19, Peter Maydell a écrit : On 29 February 2016 at 21:32, Jean-Christophe DUBOIS wrote: Le 29/02/2016 22:14, Peter Maydell a écrit : Is there a datasheet available for this? Well the SRC device is described in the i.MX6 reference manual.

Re: [Qemu-devel] [PATCH v2 7/9] i.MX: Add i.MX6 SOC implementation.

On 29 February 2016 at 21:32, Jean-Christophe DUBOIS wrote: > Le 29/02/2016 22:14, Peter Maydell a écrit : >> Is there a datasheet available for this? > Well the SRC device is described in the i.MX6 reference manual. > >

Re: [Qemu-devel] [PATCH v2 7/9] i.MX: Add i.MX6 SOC implementation.

Le 29/02/2016 22:14, Peter Maydell a écrit : On 29 February 2016 at 20:34, Jean-Christophe DUBOIS wrote: Le 29/02/2016 18:58, Peter Maydell a écrit : To answer the question of "which of these is the correct thing to do" we need to look at what the real hardware does when

Re: [Qemu-devel] [PATCH v2 7/9] i.MX: Add i.MX6 SOC implementation.

On 29 February 2016 at 20:34, Jean-Christophe DUBOIS wrote: > Le 29/02/2016 18:58, Peter Maydell a écrit : >> To answer the question of "which of these is the correct thing to do" >> we need to look at what the real hardware does when it's running Linux: >> does it run Linux

Re: [Qemu-devel] [PATCH v2 7/9] i.MX: Add i.MX6 SOC implementation.

Le 29/02/2016 18:58, Peter Maydell a écrit : On 19 February 2016 at 06:32, Jean-Christophe DUBOIS wrote: If I set has_el3 to false, I can boot the 4 cores without problem. With has_el3 set to true (default value) I am getting the above behavior (boot OK in uniprocessor

Re: [Qemu-devel] [PATCH v2 7/9] i.MX: Add i.MX6 SOC implementation.

On 19 February 2016 at 06:32, Jean-Christophe DUBOIS wrote: > If I set has_el3 to false, I can boot the 4 cores without problem. With > has_el3 set to true (default value) I am getting the above behavior (boot OK > in uniprocessor mode, and misbehaving if -smp >= 2). I

Re: [Qemu-devel] [PATCH v2 7/9] i.MX: Add i.MX6 SOC implementation.

Le 21/02/2016 04:42, Peter Crosthwaite a écrit : On Sat, Feb 20, 2016 at 10:03 AM, Jean-Christophe DUBOIS wrote: Le 20/02/2016 16:30, Peter Crosthwaite a écrit : On Sat, Feb 20, 2016 at 2:55 AM, Jean-Christophe DUBOIS wrote: Just to compare I

Re: [Qemu-devel] [PATCH v2 7/9] i.MX: Add i.MX6 SOC implementation.

On Sat, Feb 20, 2016 at 10:03 AM, Jean-Christophe DUBOIS wrote: > Le 20/02/2016 16:30, Peter Crosthwaite a écrit : >> >> On Sat, Feb 20, 2016 at 2:55 AM, Jean-Christophe DUBOIS >> wrote: >>> >>> Just to compare I tried to run Linux on QEMU emulating

Re: [Qemu-devel] [PATCH v2 7/9] i.MX: Add i.MX6 SOC implementation.

Le 20/02/2016 16:30, Peter Crosthwaite a écrit : On Sat, Feb 20, 2016 at 2:55 AM, Jean-Christophe DUBOIS wrote: Just to compare I tried to run Linux on QEMU emulating highbank. For now I am unable to start in SMP mode. Only one core is activated. This is probably due

Re: [Qemu-devel] [PATCH v2 7/9] i.MX: Add i.MX6 SOC implementation.

On Sat, Feb 20, 2016 at 2:55 AM, Jean-Christophe DUBOIS wrote: > Just to compare I tried to run Linux on QEMU emulating highbank. > > For now I am unable to start in SMP mode. Only one core is activated. > This is probably due to the fact that the PSCI command encodings for

Re: [Qemu-devel] [PATCH v2 7/9] i.MX: Add i.MX6 SOC implementation.

Just to compare I tried to run Linux on QEMU emulating highbank. For now I am unable to start in SMP mode. Only one core is activated. And there is linux backtrace in L2C-310 init. My command line: # qemu-system-arm -smp 4 -M highbank -m 1024M -display none -no-reboot -kernel zImage -initrd

Re: [Qemu-devel] [PATCH v2 7/9] i.MX: Add i.MX6 SOC implementation.

Le 19/02/2016 10:32, Peter Maydell a écrit : On 19 February 2016 at 06:32, Jean-Christophe DUBOIS wrote: Le 18/02/2016 22:46, Peter Maydell a écrit : Does SMP work with EL3 not enabled, or is this a different bug? If I set has_el3 to false, I can boot the 4 cores

Re: [Qemu-devel] [PATCH v2 7/9] i.MX: Add i.MX6 SOC implementation.

On 19 February 2016 at 06:32, Jean-Christophe DUBOIS wrote: > Le 18/02/2016 22:46, Peter Maydell a écrit : >> Does SMP work with EL3 not enabled, or is this a different bug? > > > If I set has_el3 to false, I can boot the 4 cores without problem. With > has_el3 set to true

Re: [Qemu-devel] [PATCH v2 7/9] i.MX: Add i.MX6 SOC implementation.

Le 18/02/2016 22:46, Peter Maydell a écrit : On 18 February 2016 at 20:51, Jean-Christophe DUBOIS wrote: Le 16/02/2016 22:57, Peter Maydell a écrit : On 16 February 2016 at 21:47, Jean-Christophe DUBOIS wrote: In QEMU, other Cortex A9

Re: [Qemu-devel] [PATCH v2 7/9] i.MX: Add i.MX6 SOC implementation.

On 18 February 2016 at 20:51, Jean-Christophe DUBOIS wrote: > Le 16/02/2016 22:57, Peter Maydell a écrit : > > On 16 February 2016 at 21:47, Jean-Christophe DUBOIS > wrote: > > In QEMU, other Cortex A9 (Versatilepb.c, Exynos, Zynq ...) are also setting

Re: [Qemu-devel] [PATCH v2 7/9] i.MX: Add i.MX6 SOC implementation.

Le 16/02/2016 22:57, Peter Maydell a écrit : On 16 February 2016 at 21:47, Jean-Christophe DUBOIS wrote: In QEMU, other Cortex A9 (Versatilepb.c, Exynos, Zynq ...) are also setting has_el3 to false ... So these generally are the "legacy" platforms which were added before

Re: [Qemu-devel] [PATCH v2 7/9] i.MX: Add i.MX6 SOC implementation.

On 16 February 2016 at 21:47, Jean-Christophe DUBOIS wrote: > In QEMU, other Cortex A9 (Versatilepb.c, Exynos, Zynq ...) are also setting > has_el3 to false ... So these generally are the "legacy" platforms which were added before we ever had EL3 support in QEMU. For them

Re: [Qemu-devel] [PATCH v2 7/9] i.MX: Add i.MX6 SOC implementation.

Le 16/02/2016 22:06, Peter Maydell a écrit : On 16 February 2016 at 20:49, Jean-Christophe DUBOIS wrote: Le 16/02/2016 16:31, Peter Maydell a écrit : On 8 February 2016 at 22:08, Jean-Christophe Dubois wrote: +

Re: [Qemu-devel] [PATCH v2 7/9] i.MX: Add i.MX6 SOC implementation.

On 16 February 2016 at 20:49, Jean-Christophe DUBOIS wrote: > Le 16/02/2016 16:31, Peter Maydell a écrit : >> On 8 February 2016 at 22:08, Jean-Christophe Dubois >> wrote: >>> +object_property_set_bool(OBJECT(>cpu[i]), false, >>> +

Re: [Qemu-devel] [PATCH v2 7/9] i.MX: Add i.MX6 SOC implementation.

Le 16/02/2016 16:31, Peter Maydell a écrit : On 8 February 2016 at 22:08, Jean-Christophe Dubois wrote: For now we only support the following devices: * up to 4 Cortex A9 cores * A9 MPCORE (SCU, GIC, TWD) * 5 i.MX UARTs * 2 EPIT timers * 1 GPT timer * 3 I2C controllers *

Re: [Qemu-devel] [PATCH v2 7/9] i.MX: Add i.MX6 SOC implementation.

On 8 February 2016 at 22:08, Jean-Christophe Dubois wrote: > For now we only support the following devices: > * up to 4 Cortex A9 cores > * A9 MPCORE (SCU, GIC, TWD) > * 5 i.MX UARTs > * 2 EPIT timers > * 1 GPT timer > * 3 I2C controllers > * 7 GPIO controllers > * 6 SDHC

[Qemu-devel] [PATCH v2 7/9] i.MX: Add i.MX6 SOC implementation.

For now we only support the following devices: * up to 4 Cortex A9 cores * A9 MPCORE (SCU, GIC, TWD) * 5 i.MX UARTs * 2 EPIT timers * 1 GPT timer * 3 I2C controllers * 7 GPIO controllers * 6 SDHC controllers * 1 CCM device * 1 SRC device * various ROM/RAM areas. Signed-off-by: Jean-Christophe