Re: [Qemu-devel] [PATCH v3] target-tilegx: Support iret instruction and related special registers

2015-10-02 Thread Chris Metcalf
On 10/1/2015 10:26 PM, Richard Henderson wrote: On 10/02/2015 11:31 AM, Chris Metcalf wrote: It disables interrupts from being delivered. This means asynchronous interrupts get deferred until ICS is set back to zero, and synchronous interrupts (page fault, etc) cause a double-fault instead.

[Qemu-devel] [PATCH v3] target-tilegx: Support iret instruction and related special registers

2015-10-01 Thread gang . chen . 5i5j
From: Chen Gang Acording to the __longjmp tilegx libc implementation, and reference from tilegx ISA document, and suggested by tilegx architecture member, we can treat iret instruction as "jrp lr". The related code is below: ENTRY (__longjmp)

Re: [Qemu-devel] [PATCH v3] target-tilegx: Support iret instruction and related special registers

2015-10-01 Thread Richard Henderson
On 10/01/2015 10:37 PM, gang.chen.5...@gmail.com wrote: { mtspr INTERRUPT_CRITICAL_SECTION, r3 shli r2, r2, SPR_EX_CONTEXT_0_1__ICS_SHIFT } { mtspr EX_CONTEXT_0_0, lr ori r2, r2, RETURN_PL } {

Re: [Qemu-devel] [PATCH v3] target-tilegx: Support iret instruction and related special registers

2015-10-01 Thread Chen Gang
On 10/2/15 08:36, Richard Henderson wrote: > On 10/01/2015 10:37 PM, gang.chen.5...@gmail.com wrote: >> { >> mtspr INTERRUPT_CRITICAL_SECTION, r3 >> shli r2, r2, SPR_EX_CONTEXT_0_1__ICS_SHIFT >> } >> >> { >> mtspr EX_CONTEXT_0_0, lr >> ori r2, r2, RETURN_PL >> } >> >> { >> or r0, r1, r0 >> mtspr

Re: [Qemu-devel] [PATCH v3] target-tilegx: Support iret instruction and related special registers

2015-10-01 Thread Chris Metcalf
On 10/1/2015 8:36 PM, Richard Henderson wrote: On 10/01/2015 10:37 PM, gang.chen.5...@gmail.com wrote: { mtspr INTERRUPT_CRITICAL_SECTION, r3 shli r2, r2, SPR_EX_CONTEXT_0_1__ICS_SHIFT } { mtspr EX_CONTEXT_0_0, lr ori

Re: [Qemu-devel] [PATCH v3] target-tilegx: Support iret instruction and related special registers

2015-10-01 Thread Chen Gang
OK, thanks. I shall try to send patch v4 for it within 2 days. On 10/2/15 09:31, Chris Metcalf wrote: > On 10/1/2015 8:36 PM, Richard Henderson wrote: >> On 10/01/2015 10:37 PM, gang.chen.5...@gmail.com wrote: >>> { >>>mtspr INTERRUPT_CRITICAL_SECTION, r3 >>>

Re: [Qemu-devel] [PATCH v3] target-tilegx: Support iret instruction and related special registers

2015-10-01 Thread Richard Henderson
On 10/02/2015 11:31 AM, Chris Metcalf wrote: It disables interrupts from being delivered. This means asynchronous interrupts get deferred until ICS is set back to zero, and synchronous interrupts (page fault, etc) cause a double-fault instead. ICS is automatically set on entry to interrupt