Re: [Qemu-devel] [PATCH v3 06/16] hw/intc/arm_gic: Add Interrupt Group Registers

2015-04-20 Thread Edgar E. Iglesias
On Wed, Apr 15, 2015 at 11:02:12AM -0500, Greg Bellows wrote: > From: Fabian Aggeler > > Interrupt Group Registers (previously called Interrupt Security > Registers) as defined in GICv1 with Security Extensions or GICv2 allow > to configure interrupts as Secure (Group0) or Non-secure (Group1). >

[Qemu-devel] [PATCH v3 06/16] hw/intc/arm_gic: Add Interrupt Group Registers

2015-04-15 Thread Greg Bellows
From: Fabian Aggeler Interrupt Group Registers (previously called Interrupt Security Registers) as defined in GICv1 with Security Extensions or GICv2 allow to configure interrupts as Secure (Group0) or Non-secure (Group1). In GICv2 these registers are implemented independent of the existence of S