Re: [Qemu-devel] [PATCH v3 1/2] nvic: Handle ARMv6-M SCS reserved registers

2018-07-06 Thread Peter Maydell
On 5 July 2018 at 23:21, Julia Suvorova wrote: > Handle SCS reserved registers listed in ARMv6-M ARM D3.6.1. > All reserved registers are RAZ/WI. ARM_FEATURE_M_MAIN is used for the > checks, because these registers are reserved in ARMv8-M Baseline too. > > Signed-off-by: Julia Suvorova > --- > h

[Qemu-devel] [PATCH v3 1/2] nvic: Handle ARMv6-M SCS reserved registers

2018-07-05 Thread Julia Suvorova via Qemu-devel
Handle SCS reserved registers listed in ARMv6-M ARM D3.6.1. All reserved registers are RAZ/WI. ARM_FEATURE_M_MAIN is used for the checks, because these registers are reserved in ARMv8-M Baseline too. Signed-off-by: Julia Suvorova --- hw/intc/armv7m_nvic.c | 51 +++