Re: [Qemu-devel] [PATCH v3 1/3] hw/misc: Add a model for the ASPEED System Control Unit

2016-06-27 Thread Andrew Jeffery
On Mon, 2016-06-27 at 14:42 +0100, Peter Maydell wrote: > On 24 June 2016 at 05:58, Andrew Jeffery wrote: > > > > The SCU is a collection of chip-level control registers that manage the > > various functions supported by ASPEED SoCs. Typically the bits control > > interactions

Re: [Qemu-devel] [PATCH v3 1/3] hw/misc: Add a model for the ASPEED System Control Unit

2016-06-27 Thread Peter Maydell
On 24 June 2016 at 05:58, Andrew Jeffery wrote: > The SCU is a collection of chip-level control registers that manage the > various functions supported by ASPEED SoCs. Typically the bits control > interactions with clocks, external hardware or reset behaviour, and we > can largly

[Qemu-devel] [PATCH v3 1/3] hw/misc: Add a model for the ASPEED System Control Unit

2016-06-23 Thread Andrew Jeffery
The SCU is a collection of chip-level control registers that manage the various functions supported by ASPEED SoCs. Typically the bits control interactions with clocks, external hardware or reset behaviour, and we can largly take a hands-off approach to reads and writes. Firmware makes heavy use