This should be squashed with 9/32.
On 10 June 2014 18:54, Fabian Aggeler wrote:
> If EL3 is using Aarch64 IRQ/FIQ masking is ignored in
> all exception levels other than EL3 if SCR.{FIQ|IRQ} is
> set to 1 (routed to EL3).
>
> Signed-off-by: Fabian Aggeler
> ---
> target-arm/cpu.h | 98
> +
If EL3 is using Aarch64 IRQ/FIQ masking is ignored in
all exception levels other than EL3 if SCR.{FIQ|IRQ} is
set to 1 (routed to EL3).
Signed-off-by: Fabian Aggeler
---
target-arm/cpu.h | 98 +---
1 file changed, 72 insertions(+), 26 deletions
