On 26 February 2014 06:33, Hu Tao hu...@cn.fujitsu.com wrote:
On Sat, Feb 15, 2014 at 04:07:05PM +, Peter Maydell wrote:
...
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 06953ac..7cbe69b 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -173,10 +173,8 @@ typedef struct
On Sat, Feb 15, 2014 at 04:07:05PM +, Peter Maydell wrote:
...
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 06953ac..7cbe69b 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -173,10 +173,8 @@ typedef struct CPUARMState {
uint32_t c1_coproc; /* Coprocessor
Implement the AArch64 TTBR* registers. For v7 these were already 64 bits
to handle LPAE, but implemented as two separate uint32_t fields.
Combine them into a single uint64_t which can be used for all purposes.
Since this requires touching every use, take the opportunity to rename
the field to the
