From: Sergey Fedorov <s.fedo...@samsung.com> Signed-off-by: Sergey Fedorov <s.fedo...@samsung.com> Signed-off-by: Fabian Aggeler <aggel...@ethz.ch> --- target-arm/cpu.h | 1 + target-arm/helper.c | 3 +++ 2 files changed, 4 insertions(+)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index bc9edaa..c76a31c 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -182,6 +182,7 @@ typedef struct CPUARMState { uint64_t c1_coproc; /* Coprocessor access register. */ uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ uint32_t c1_scr; /* secure config register. */ + uint32_t c1_sder; /* Secure debug enable register. */ uint32_t c1_nsacr; /* Non-secure access control register. */ uint64_t ttbr0_el1; /* MMU translation table base 0. */ uint64_t ttbr1_el1; /* MMU translation table base 1. */ diff --git a/target-arm/helper.c b/target-arm/helper.c index 9671f9f..4bf203e 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2279,6 +2279,9 @@ static const ARMCPRegInfo security_cp_reginfo[] = { { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3), .resetvalue = 0, }, + { .name = "SDER", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 1, + .access = PL3_RW, .resetvalue = 0, + .fieldoffset = offsetof(CPUARMState, cp15.c1_sder) }, { .name = "NSACR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 2, .access = PL3_RW | PL1_R, .resetvalue = 0, .writefn = nsacr_write, .readfn = nsacr_read, -- 1.8.3.2