Re: [Qemu-devel] [PATCH v3 2/2] target/i386: Add support for save/load IA32_UMWAIT_CONTROL MSR

2019-06-18 Thread Tao Xu
On 6/17/2019 11:39 AM, Xiaoyao Li wrote: On 6/16/2019 11:35 PM, Tao Xu wrote: UMWAIT and TPAUSE instructions use IA32_UMWAIT_CONTROL at MSR index E1H to determines the maximum time in TSC-quanta that the processor can reside in either C0.1 or C0.2. This patch is to Add support for save/load I

Re: [Qemu-devel] [PATCH v3 2/2] target/i386: Add support for save/load IA32_UMWAIT_CONTROL MSR

2019-06-16 Thread Xiaoyao Li
On 6/16/2019 11:35 PM, Tao Xu wrote: UMWAIT and TPAUSE instructions use IA32_UMWAIT_CONTROL at MSR index E1H to determines the maximum time in TSC-quanta that the processor can reside in either C0.1 or C0.2. This patch is to Add support for save/load IA32_UMWAIT_CONTROL MSR in guest. Co-deve

[Qemu-devel] [PATCH v3 2/2] target/i386: Add support for save/load IA32_UMWAIT_CONTROL MSR

2019-06-16 Thread Tao Xu
UMWAIT and TPAUSE instructions use IA32_UMWAIT_CONTROL at MSR index E1H to determines the maximum time in TSC-quanta that the processor can reside in either C0.1 or C0.2. This patch is to Add support for save/load IA32_UMWAIT_CONTROL MSR in guest. Co-developed-by: Jingqi Liu Signed-off-by: Jingq