Alexander Graf writes:
> On 05/07/2014 12:19 PM, Greg Kurz wrote:
> The uglyness about the current_cpu bit is that devices are usually not
> supposed to know about the cpu accesses come from usually. But then
> again devices shouldn't know about the endianness of a cpu either so I
> guess it's
On 05/07/2014 02:40 PM, Greg Kurz wrote:
On Wed, 07 May 2014 13:54:36 +0200
Alexander Graf wrote:
On 05/07/2014 12:19 PM, Greg Kurz wrote:
On Wed, 7 May 2014 11:41:10 +0200
Alexander Graf wrote:
Am 07.05.2014 um 11:26 schrieb Peter Maydell :
On 7 May 2014 10:09, Alexander Graf wrote:
I d
On Wed, 07 May 2014 13:54:36 +0200
Alexander Graf wrote:
> On 05/07/2014 12:19 PM, Greg Kurz wrote:
> > On Wed, 7 May 2014 11:41:10 +0200
> > Alexander Graf wrote:
> >
> >>
> >>> Am 07.05.2014 um 11:26 schrieb Peter Maydell :
> >>>
> On 7 May 2014 10:09, Alexander Graf wrote:
> I don't
On 05/07/2014 12:19 PM, Greg Kurz wrote:
On Wed, 7 May 2014 11:41:10 +0200
Alexander Graf wrote:
Am 07.05.2014 um 11:26 schrieb Peter Maydell :
On 7 May 2014 10:09, Alexander Graf wrote:
I don't think we should overengineer hacks for legacy virtio.
Agreed. So what's our final conclusion:
On Wed, 7 May 2014 11:41:10 +0200
Alexander Graf wrote:
>
>
> > Am 07.05.2014 um 11:26 schrieb Peter Maydell :
> >
> >> On 7 May 2014 10:09, Alexander Graf wrote:
> >> I don't think we should overengineer hacks for legacy virtio.
> >
> > Agreed. So what's our final conclusion: virtio endiann
> Am 07.05.2014 um 11:40 schrieb Peter Maydell :
>
>> On 7 May 2014 10:37, Alexander Graf wrote:
>>
>>
Am 07.05.2014 um 11:26 schrieb Peter Maydell :
On 7 May 2014 10:09, Alexander Graf wrote:
I don't think we should overengineer hacks for legacy virtio.
>>>
>>> Agreed.
> Am 07.05.2014 um 11:26 schrieb Peter Maydell :
>
>> On 7 May 2014 10:09, Alexander Graf wrote:
>> I don't think we should overengineer hacks for legacy virtio.
>
> Agreed. So what's our final conclusion: virtio endianness
> is the endianness of the guest kernel at the point where
> it trigge
On 7 May 2014 10:37, Alexander Graf wrote:
>
>
>> Am 07.05.2014 um 11:26 schrieb Peter Maydell :
>>
>>> On 7 May 2014 10:09, Alexander Graf wrote:
>>> I don't think we should overengineer hacks for legacy virtio.
>>
>> Agreed. So what's our final conclusion: virtio endianness
>> is the endianness
> Am 07.05.2014 um 11:26 schrieb Peter Maydell :
>
>> On 7 May 2014 10:09, Alexander Graf wrote:
>> I don't think we should overengineer hacks for legacy virtio.
>
> Agreed. So what's our final conclusion: virtio endianness
> is the endianness of the guest kernel at the point where
> it trigge
On 7 May 2014 10:09, Alexander Graf wrote:
> I don't think we should overengineer hacks for legacy virtio.
Agreed. So what's our final conclusion: virtio endianness
is the endianness of the guest kernel at the point where
it triggers a reset of the virtio device, yes?
thanks
-- PMM
On 07.05.14 10:14, Greg Kurz wrote:
On Tue, 6 May 2014 19:37:22 +0100
Peter Maydell wrote:
On 5 May 2014 09:07, Greg Kurz wrote:
POWER7, POWER7+ and POWER8 families use the ILE bit of the LPCR
special purpose register to decide the endianness to use when
entering interrupt handlers. When run
On 7 May 2014 09:14, Greg Kurz wrote:
> On Tue, 6 May 2014 19:37:22 +0100
> Peter Maydell wrote:
>> On 5 May 2014 09:07, Greg Kurz wrote:
>> > POWER7, POWER7+ and POWER8 families use the ILE bit of the LPCR
>> > special purpose register to decide the endianness to use when
>> > entering interrup
On Tue, 6 May 2014 19:37:22 +0100
Peter Maydell wrote:
> On 5 May 2014 09:07, Greg Kurz wrote:
> > POWER7, POWER7+ and POWER8 families use the ILE bit of the LPCR
> > special purpose register to decide the endianness to use when
> > entering interrupt handlers. When running a Linux guest, this
>
On 5 May 2014 09:07, Greg Kurz wrote:
> POWER7, POWER7+ and POWER8 families use the ILE bit of the LPCR
> special purpose register to decide the endianness to use when
> entering interrupt handlers. When running a Linux guest, this
> provides a hint on the endianness used by the kernel. From a
> Q
POWER7, POWER7+ and POWER8 families use the ILE bit of the LPCR
special purpose register to decide the endianness to use when
entering interrupt handlers. When running a Linux guest, this
provides a hint on the endianness used by the kernel. From a
QEMU point of view, the information is needed for
POWER7, POWER7+ and POWER8 families use the ILE bit of the LPCR
special purpose register to decide the endianness to use when
entering interrupt handlers. When running a Linux guest, this
provides a hint on the endianness used by the kernel. From a
QEMU point of view, the information is needed for
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