> The only commands that have the 5th bit required to address XR16 are
> S32M2I/S32I2M.
>
> I can split it out into a separate utility function and put a conditional
> into the S32M2I/S32I2M functions if you are more comfortable with that.
It is not a bad idea. (preventing all instructions
The only commands that have the 5th bit required to address XR16 are
S32M2I/S32I2M.
I can split it out into a separate utility function and put a conditional into
the S32M2I/S32I2M functions if you are more comfortable with that.
-Original Message-
From: Aleksandar Markovic
Sent:
> > This does not handle the case xra == XR16.
> I do not see where the case is un-handled. XR16 maps to index 15 in the
> mxu_gpr array.
But, XR16 has its own rules for read/write, and you are treating it just as a
regular register.
What happens if reg > 16? Also, the argument reg should be unsigned.
If rev > 16 the instruction is invalid. What type of error can/should I throw
here.
This does not handle the case xra == XR16. From the doc:
I do not see where the case is un-handled. XR16 maps to index 15 in the mxu_gpr
> From: Craig Janeczek
> Sent: Tuesday, August 28, 2018 3:00 PM
> To: qemu-devel@nongnu.org
> Cc: Aleksandar Markovic; aurel...@aurel32.net; Craig Janeczek
> Subject: [PATCH v3 3/8] target/mips: Add MXU instructions S32I2M and S32M2I
>
> This commit makes the MXU registers and the utility
This commit makes the MXU registers and the utility functions for
reading/writing to them. This is required for full MXU instruction
support.
Adds support for emulating the S32I2M and S32M2I MXU instructions.
Signed-off-by: Craig Janeczek
---
v1
- initial patch
v2
- Fix checkpatch.pl
