On 09/15/2016 10:48 AM, Alex Bennée wrote:
Ahh ok. The ARM code just allocates temps on demand including for its
zero register which I guess means multiple ones could be assigned. There
is also temp allocation logic to free them at the end of the block.
I wonder if this is something that should
Richard Henderson writes:
> On 09/15/2016 07:38 AM, Alex Bennée wrote:
>>> +lab_fail = gen_new_label();
>>> > +lab_done = gen_new_label();
>>> > +tcg_gen_brcond_i64(TCG_COND_NE, addr, cpu_lock_addr, lab_fail);
>>> > +tcg_temp_free_i64(addr);
>>> >
>>> > -lab_fail = gen_ne
On 09/15/2016 07:38 AM, Alex Bennée wrote:
+lab_fail = gen_new_label();
> +lab_done = gen_new_label();
> +tcg_gen_brcond_i64(TCG_COND_NE, addr, cpu_lock_addr, lab_fail);
> +tcg_temp_free_i64(addr);
>
> -lab_fail = gen_new_label();
> -lab_done = gen_new_label();
> -
Richard Henderson writes:
> Emulating LL/SC with cmpxchg is not correct, since it can
> suffer from the ABA problem. However, portable parallel
> code is writting assuming only cmpxchg which means that in
> practice this is a viable alternative.
>
> Signed-off-by: Richard Henderson
> ---
> li
Emulating LL/SC with cmpxchg is not correct, since it can
suffer from the ABA problem. However, portable parallel
code is writting assuming only cmpxchg which means that in
practice this is a viable alternative.
Signed-off-by: Richard Henderson
---
linux-user/main.c| 49 ---
