On 17.09.2011, at 23:40, Blue Swirl wrote:
On Thu, Sep 15, 2011 at 11:31 AM, Avi Kivity a...@redhat.com wrote:
On 09/15/2011 01:01 PM, Benjamin Herrenschmidt wrote:
Sure :). So the problem is that when emulating the G3 Beige machine in
QEMU (default ppc32 target) we also add a PCI VGA
On 09/19/2011 12:15 PM, Alexander Graf wrote:
On 17.09.2011, at 23:40, Blue Swirl wrote:
On Thu, Sep 15, 2011 at 11:31 AM, Avi Kivitya...@redhat.com wrote:
On 09/15/2011 01:01 PM, Benjamin Herrenschmidt wrote:
Sure :). So the problem is that when emulating the G3 Beige machine in
On 19.09.2011, at 11:22, Avi Kivity wrote:
On 09/19/2011 12:15 PM, Alexander Graf wrote:
On 17.09.2011, at 23:40, Blue Swirl wrote:
On Thu, Sep 15, 2011 at 11:31 AM, Avi Kivitya...@redhat.com wrote:
On 09/15/2011 01:01 PM, Benjamin Herrenschmidt wrote:
Sure :). So the problem is
On 09/19/2011 12:36 PM, Alexander Graf wrote:
8088-808f : macio
0006-0007 : macio-nvram
0002-00020fff : pmac-ide
00016000-00017fff : cuda
00013000-0001303f : escc-bar
8000-8fff : dbdma
-0fff : heathrow-pic
On 09/18/2011 12:40 AM, Blue Swirl wrote:
On Thu, Sep 15, 2011 at 11:31 AM, Avi Kivitya...@redhat.com wrote:
On 09/15/2011 01:01 PM, Benjamin Herrenschmidt wrote:
Sure :). So the problem is that when emulating the G3 Beige machine in
QEMU (default ppc32 target) we also add a PCI
On Thu, Sep 15, 2011 at 11:31 AM, Avi Kivity a...@redhat.com wrote:
On 09/15/2011 01:01 PM, Benjamin Herrenschmidt wrote:
Sure :). So the problem is that when emulating the G3 Beige machine in
QEMU (default ppc32 target) we also add a PCI VGA adapter. Apparently,
on x86 that PCI VGA
On 09/14/2011 11:25 PM, Blue Swirl wrote:
On Wed, Sep 14, 2011 at 8:15 PM, Avi Kivitya...@redhat.com wrote:
On 09/14/2011 11:06 PM, Blue Swirl wrote:
On Wed, Sep 14, 2011 at 8:35 AM, Avi Kivitya...@redhat.comwrote:
On 09/14/2011 11:27 AM, Alexander Graf wrote:
On
On 09/15/2011 04:24 AM, Benjamin Herrenschmidt wrote:
On Wed, 2011-09-14 at 23:41 +0200, Alexander Graf wrote:
On 14.09.2011, at 22:42, Richard Henderson wrote:
On 09/14/2011 01:35 PM, Alexander Graf wrote:
Can you explain what the memory map looks like from the hardware
point of
On 15.09.2011, at 03:24, Benjamin Herrenschmidt wrote:
On Wed, 2011-09-14 at 23:41 +0200, Alexander Graf wrote:
On 14.09.2011, at 22:42, Richard Henderson wrote:
On 09/14/2011 01:35 PM, Alexander Graf wrote:
Can you explain what the memory map looks like from the hardware
point of view?
Sure :). So the problem is that when emulating the G3 Beige machine in
QEMU (default ppc32 target) we also add a PCI VGA adapter. Apparently,
on x86 that PCI VGA adapter can map the special VGA regions to
somewhere, namely 0xa. With the memory api overhaul, this also
slipped into the PPC
On 09/15/2011 01:01 PM, Benjamin Herrenschmidt wrote:
Sure :). So the problem is that when emulating the G3 Beige machine in
QEMU (default ppc32 target) we also add a PCI VGA adapter. Apparently,
on x86 that PCI VGA adapter can map the special VGA regions to
somewhere, namely 0xa.
On 09/13/2011 10:39 PM, Blue Swirl wrote:
Here is the problem: Both the vram and the ISA range get mapped into
system address space, but the former eclipses the latter as it shows up
earlier in the list and has the same priority. This picture changes with
the chain-4 alias which has
On 14.09.2011, at 09:11, Avi Kivity wrote:
On 09/13/2011 10:39 PM, Blue Swirl wrote:
Here is the problem: Both the vram and the ISA range get mapped into
system address space, but the former eclipses the latter as it shows up
earlier in the list and has the same priority. This
On 2011-09-14 09:42, Alexander Graf wrote:
On 14.09.2011, at 09:11, Avi Kivity wrote:
On 09/13/2011 10:39 PM, Blue Swirl wrote:
Here is the problem: Both the vram and the ISA range get mapped into
system address space, but the former eclipses the latter as it shows up
earlier in the
On 09/14/2011 10:42 AM, Alexander Graf wrote:
On 14.09.2011, at 09:11, Avi Kivity wrote:
On 09/13/2011 10:39 PM, Blue Swirl wrote:
Here is the problem: Both the vram and the ISA range get mapped into
system address space, but the former eclipses the latter as it shows up
On 2011-09-14 10:17, Avi Kivity wrote:
On 09/14/2011 10:42 AM, Alexander Graf wrote:
On 14.09.2011, at 09:11, Avi Kivity wrote:
On 09/13/2011 10:39 PM, Blue Swirl wrote:
Here is the problem: Both the vram and the ISA range get mapped into
system address space, but the former
On 09/14/2011 11:20 AM, Jan Kiszka wrote:
Anyway PCI supports the vga region at 0xa-0xc. Where is it
supposed to be mapped?
...but not all PCI bridges make use of this feature / forward legacy
requests.
Then this should be fixed in the bridge?
--
error compiling committee.c:
On 2011-09-14 10:22, Avi Kivity wrote:
On 09/14/2011 11:20 AM, Jan Kiszka wrote:
Anyway PCI supports the vga region at 0xa-0xc. Where is it
supposed to be mapped?
...but not all PCI bridges make use of this feature / forward legacy
requests.
Then this should be fixed in the
On 14.09.2011, at 10:24, Jan Kiszka wrote:
On 2011-09-14 10:22, Avi Kivity wrote:
On 09/14/2011 11:20 AM, Jan Kiszka wrote:
Anyway PCI supports the vga region at 0xa-0xc. Where is it
supposed to be mapped?
...but not all PCI bridges make use of this feature / forward legacy
On 2011-09-14 10:27, Alexander Graf wrote:
On 14.09.2011, at 10:24, Jan Kiszka wrote:
On 2011-09-14 10:22, Avi Kivity wrote:
On 09/14/2011 11:20 AM, Jan Kiszka wrote:
Anyway PCI supports the vga region at 0xa-0xc. Where is it
supposed to be mapped?
...but not all PCI bridges
On 09/14/2011 11:27 AM, Alexander Graf wrote:
On 14.09.2011, at 10:24, Jan Kiszka wrote:
On 2011-09-14 10:22, Avi Kivity wrote:
On 09/14/2011 11:20 AM, Jan Kiszka wrote:
Anyway PCI supports the vga region at 0xa-0xc. Where is it
supposed to be mapped?
...but not all PCI
On Wed, Sep 14, 2011 at 8:35 AM, Avi Kivity a...@redhat.com wrote:
On 09/14/2011 11:27 AM, Alexander Graf wrote:
On 14.09.2011, at 10:24, Jan Kiszka wrote:
On 2011-09-14 10:22, Avi Kivity wrote:
On 09/14/2011 11:20 AM, Jan Kiszka wrote:
Anyway PCI supports the vga region at
On 14.09.2011, at 22:06, Blue Swirl wrote:
On Wed, Sep 14, 2011 at 8:35 AM, Avi Kivity a...@redhat.com wrote:
On 09/14/2011 11:27 AM, Alexander Graf wrote:
On 14.09.2011, at 10:24, Jan Kiszka wrote:
On 2011-09-14 10:22, Avi Kivity wrote:
On 09/14/2011 11:20 AM, Jan Kiszka wrote:
On 09/14/2011 11:06 PM, Blue Swirl wrote:
On Wed, Sep 14, 2011 at 8:35 AM, Avi Kivitya...@redhat.com wrote:
On 09/14/2011 11:27 AM, Alexander Graf wrote:
On 14.09.2011, at 10:24, Jan Kiszka wrote:
On 2011-09-14 10:22, Avi Kivity wrote:
On 09/14/2011 11:20 AM, Jan Kiszka wrote:
On 09/14/2011 11:14 PM, Alexander Graf wrote:
(assuming I understood the problem correctly - not sure)
I think you did.
Well I don't completely, so would anybody who feels reasonably savvy in messing
with the new memory api like to step up and implement this? :)
Can you explain what
On Wed, Sep 14, 2011 at 8:15 PM, Avi Kivity a...@redhat.com wrote:
On 09/14/2011 11:06 PM, Blue Swirl wrote:
On Wed, Sep 14, 2011 at 8:35 AM, Avi Kivitya...@redhat.com wrote:
On 09/14/2011 11:27 AM, Alexander Graf wrote:
On 14.09.2011, at 10:24, Jan Kiszka wrote:
On 2011-09-14
Am 14.09.2011 um 22:16 schrieb Avi Kivity a...@redhat.com:
On 09/14/2011 11:14 PM, Alexander Graf wrote:
(assuming I understood the problem correctly - not sure)
I think you did.
Well I don't completely, so would anybody who feels reasonably savvy in
messing with the new memory api
On 09/14/2011 01:35 PM, Alexander Graf wrote:
Can you explain what the memory map looks like from the hardware point of
view?
If you can tell me where to find out :). I seriously have zero experience in
VGA mapping - and it sounds as if Blue has a pretty good idea what's going on.
He's
Am 14.09.2011 um 22:42 schrieb Richard Henderson:
On 09/14/2011 01:35 PM, Alexander Graf wrote:
Can you explain what the memory map looks like from the hardware
point of view?
If you can tell me where to find out :). I seriously have zero
experience in VGA mapping - and it sounds as if
On 14.09.2011, at 22:42, Richard Henderson wrote:
On 09/14/2011 01:35 PM, Alexander Graf wrote:
Can you explain what the memory map looks like from the hardware point of
view?
If you can tell me where to find out :). I seriously have zero experience in
VGA mapping - and it sounds as
On Wed, 2011-09-14 at 23:41 +0200, Alexander Graf wrote:
On 14.09.2011, at 22:42, Richard Henderson wrote:
On 09/14/2011 01:35 PM, Alexander Graf wrote:
Can you explain what the memory map looks like from the hardware
point of view?
If you can tell me where to find out :). I
On 12.09.2011, at 22:21, Blue Swirl wrote:
On Mon, Sep 12, 2011 at 3:20 PM, Alexander Graf ag...@suse.de wrote:
Jan Kiszka wrote:
Most VGA memory access modes require MMIO handling as they demand weird
logic to get a byte from or into the video RAM. However, there is one
exception: chain 4
On 12.09.2011, at 17:57, Jan Kiszka wrote:
On 2011-09-12 17:49, Jan Kiszka wrote:
On 2011-09-12 17:45, Andreas Färber wrote:
Am 12.09.2011 17:33, schrieb Jan Kiszka:
On 2011-09-12 17:20, Alexander Graf wrote:
Jan Kiszka wrote:
Most VGA memory access modes require MMIO handling as they
On 09/13/2011 09:54 AM, Alexander Graf wrote:
I had similar problems with sun4u, fixed with
f69539b14bdba7a5cd22e1f4bed439b476b17286. I think also here, PCI
should be given a memory range at 0x8000 and VGA should
automatically use that like.
Yeah, usually the ISA bus is behind an
On 13.09.2011, at 09:51, Avi Kivity wrote:
On 09/13/2011 09:54 AM, Alexander Graf wrote:
I had similar problems with sun4u, fixed with
f69539b14bdba7a5cd22e1f4bed439b476b17286. I think also here, PCI
should be given a memory range at 0x8000 and VGA should
automatically use
On 09/13/2011 10:54 AM, Alexander Graf wrote:
Yeah, usually the ISA bus is behind an ISA-PCI bridge, so it should inherit
the offset from its parent. Or do you mean something different?
He means that isa_mem_base should go away; instead isa_address_space()
should be a subregion at
On 2011-09-13 09:39, Alexander Graf wrote:
On 12.09.2011, at 17:57, Jan Kiszka wrote:
On 2011-09-12 17:49, Jan Kiszka wrote:
On 2011-09-12 17:45, Andreas Färber wrote:
Am 12.09.2011 17:33, schrieb Jan Kiszka:
On 2011-09-12 17:20, Alexander Graf wrote:
Jan Kiszka wrote:
Most VGA memory
Am 13.09.2011 um 10:14 schrieb Jan Kiszka:
On 2011-09-13 09:39, Alexander Graf wrote:
(qemu) device_show #3
dev: VGA, id #3, version 2
dev.
version_id: 0002
config: 00 00 00 00 10 d1 cf 20 - 00 00 00 00 10 d1
d0 30
...
irq_state:
On 13.09.2011, at 10:14, Jan Kiszka wrote:
On 2011-09-13 09:39, Alexander Graf wrote:
On 12.09.2011, at 17:57, Jan Kiszka wrote:
On 2011-09-12 17:49, Jan Kiszka wrote:
On 2011-09-12 17:45, Andreas Färber wrote:
Am 12.09.2011 17:33, schrieb Jan Kiszka:
On 2011-09-12 17:20, Alexander
On 2011-09-13 10:40, Alexander Graf wrote:
Btw, it still tries to execute invalid code even with your patch. #if 0'ing
out the memory region updates at least get the guest booting for me. Btw, to
get it working you also need a patch for the interrupt controller (another
breakage thanks to
On 13.09.2011, at 11:00, Jan Kiszka wrote:
On 2011-09-13 10:40, Alexander Graf wrote:
Btw, it still tries to execute invalid code even with your patch. #if 0'ing
out the memory region updates at least get the guest booting for me. Btw, to
get it working you also need a patch for the
Am 13.09.2011 um 11:00 schrieb Jan Kiszka:
On 2011-09-13 10:40, Alexander Graf wrote:
Btw, it still tries to execute invalid code even with your patch.
#if 0'ing out the memory region updates at least get the guest
booting for me. Btw, to get it working you also need a patch for
the
On 2011-09-13 11:42, Alexander Graf wrote:
On 13.09.2011, at 11:00, Jan Kiszka wrote:
On 2011-09-13 10:40, Alexander Graf wrote:
Btw, it still tries to execute invalid code even with your patch. #if 0'ing
out the memory region updates at least get the guest booting for me. Btw,
to get
On Tue, Sep 13, 2011 at 11:34 AM, Jan Kiszka jan.kis...@siemens.com wrote:
On 2011-09-13 11:42, Alexander Graf wrote:
On 13.09.2011, at 11:00, Jan Kiszka wrote:
On 2011-09-13 10:40, Alexander Graf wrote:
Btw, it still tries to execute invalid code even with your patch. #if
0'ing out the
Jan Kiszka wrote:
Most VGA memory access modes require MMIO handling as they demand weird
logic to get a byte from or into the video RAM. However, there is one
exception: chain 4 mode with all memory planes enabled for writing. This
mode actually allows lineary mapping, which can then be
On 2011-09-12 17:20, Alexander Graf wrote:
Jan Kiszka wrote:
Most VGA memory access modes require MMIO handling as they demand weird
logic to get a byte from or into the video RAM. However, there is one
exception: chain 4 mode with all memory planes enabled for writing. This
mode actually
Am 12.09.2011 17:33, schrieb Jan Kiszka:
On 2011-09-12 17:20, Alexander Graf wrote:
Jan Kiszka wrote:
Most VGA memory access modes require MMIO handling as they demand weird
logic to get a byte from or into the video RAM. However, there is one
exception: chain 4 mode with all memory planes
On 2011-09-12 17:45, Andreas Färber wrote:
Am 12.09.2011 17:33, schrieb Jan Kiszka:
On 2011-09-12 17:20, Alexander Graf wrote:
Jan Kiszka wrote:
Most VGA memory access modes require MMIO handling as they demand weird
logic to get a byte from or into the video RAM. However, there is one
On 2011-09-12 17:49, Jan Kiszka wrote:
On 2011-09-12 17:45, Andreas Färber wrote:
Am 12.09.2011 17:33, schrieb Jan Kiszka:
On 2011-09-12 17:20, Alexander Graf wrote:
Jan Kiszka wrote:
Most VGA memory access modes require MMIO handling as they demand weird
logic to get a byte from or into the
On Mon, Sep 12, 2011 at 3:20 PM, Alexander Graf ag...@suse.de wrote:
Jan Kiszka wrote:
Most VGA memory access modes require MMIO handling as they demand weird
logic to get a byte from or into the video RAM. However, there is one
exception: chain 4 mode with all memory planes enabled for
On 08/22/2011 08:12 PM, Jan Kiszka wrote:
Most VGA memory access modes require MMIO handling as they demand weird
logic to get a byte from or into the video RAM. However, there is one
exception: chain 4 mode with all memory planes enabled for writing. This
mode actually allows lineary mapping,
On 2011-08-25 09:19, Avi Kivity wrote:
On 08/22/2011 08:12 PM, Jan Kiszka wrote:
Most VGA memory access modes require MMIO handling as they demand weird
logic to get a byte from or into the video RAM. However, there is one
exception: chain 4 mode with all memory planes enabled for writing.
On 08/25/2011 12:07 PM, Jan Kiszka wrote:
On which version of grub does this work? This isn't having any effect
on my Fedora grub.
It's both grub1 (0.97) in graphical mode as used by OpenSUSE 11.4 and
grub2 (1.99-rc1) of Ubuntu 11.04.
Is Fedora's grub still slow or was it already fast
On 2011-08-25 11:16, Avi Kivity wrote:
On 08/25/2011 12:07 PM, Jan Kiszka wrote:
On which version of grub does this work? This isn't having any effect
on my Fedora grub.
It's both grub1 (0.97) in graphical mode as used by OpenSUSE 11.4 and
grub2 (1.99-rc1) of Ubuntu 11.04.
Is Fedora's
On 08/25/2011 12:21 PM, Jan Kiszka wrote:
Still slow. I tried an old F11 image I had lying around, and -snapshot
/dev/sda, but this laptop was installed many years ago. I'll download
some more images and try.
You may also want to instrument vga_update_memory_access if some
requirement
On 2011-08-25 12:45, Avi Kivity wrote:
On 08/25/2011 12:21 PM, Jan Kiszka wrote:
Still slow. I tried an old F11 image I had lying around, and -snapshot
/dev/sda, but this laptop was installed many years ago. I'll download
some more images and try.
You may also want to instrument
On 08/25/2011 01:51 PM, Jan Kiszka wrote:
Plain F15 is slow. SR2 = SR4 = 0.
So it's not using chain4 mode. Can you check what mode the adapter is
actually in and how VRAM is accessed? Likely, there is nothing we can do
about it. /me just wonders what makes F15 grub behave differently from
On 2011-08-25 13:19, Avi Kivity wrote:
On 08/25/2011 01:51 PM, Jan Kiszka wrote:
Plain F15 is slow. SR2 = SR4 = 0.
So it's not using chain4 mode. Can you check what mode the adapter is
actually in and how VRAM is accessed? Likely, there is nothing we can do
about it. /me just wonders what
Most VGA memory access modes require MMIO handling as they demand weird
logic to get a byte from or into the video RAM. However, there is one
exception: chain 4 mode with all memory planes enabled for writing. This
mode actually allows lineary mapping, which can then be combined with
dirty logging
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