On 27 December 2011 20:13, Mark Langsdorf wrote:
> +#define DEFAULT_CACHE_TYPE 0x19080800
Could use a comment saying what this actually is.
As far as I can tell it's actually specifying an invalid
I/D size for a PL310, which makes me suspicious of it.
(I might have misdecoded the bit fields, do c
From: Rob Herring
This is just a dummy device for ARM L2 cache controllers, based on the
pl310. The cache type parameter can be defined by a property value
and has a meaningful default.
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
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Changes from v2
Reformatted a couple of
