On 24 April 2012 05:19, Evgeny Voevodin e.voevo...@samsung.com wrote:
New IRQ gate consists of n_in input qdev gpio lines and one
output sysbus IRQ line. The output IRQ level is formed as OR
between all gpio inputs.
Signed-off-by: Evgeny Voevodin e.voevo...@samsung.com
Reviewed-by: Peter
On 24.04.2012 20:17, Peter Maydell wrote:
On 24 April 2012 05:19, Evgeny Voevodine.voevo...@samsung.com wrote:
New IRQ gate consists of n_in input qdev gpio lines and one
output sysbus IRQ line. The output IRQ level is formed as OR
between all gpio inputs.
Signed-off-by: Evgeny
New IRQ gate consists of n_in input qdev gpio lines and one
output sysbus IRQ line. The output IRQ level is formed as OR
between all gpio inputs.
Signed-off-by: Evgeny Voevodin e.voevo...@samsung.com
---
hw/exynos4210.c | 32 +++-
hw/exynos4210.h |2 +-
Sorry, sent an old version. New version will be in next answer.
--
Kind regards,
Evgeny Voevodin,
Leading Software Engineer,
ASWG, Moscow RD center, Samsung Electronics
e-mail: e.voevo...@samsung.com
New IRQ gate consists of n_in input qdev gpio lines and one
output sysbus IRQ line. The output IRQ level is formed as OR
between all gpio inputs.
Signed-off-by: Evgeny Voevodin e.voevo...@samsung.com
---
hw/exynos4210.c | 32 +++--
hw/exynos4210.h |2 +-
