On 24.04.2012 20:17, Peter Maydell wrote:
On 24 April 2012 05:19, Evgeny Voevodin wrote:
New IRQ gate consists of n_in input qdev gpio lines and one
output sysbus IRQ line. The output IRQ level is formed as OR
between all gpio inputs.
Signed-off-by: Evgeny Voevodin
Reviewed-by: Peter Maydell
On 24 April 2012 05:19, Evgeny Voevodin wrote:
> New IRQ gate consists of n_in input qdev gpio lines and one
> output sysbus IRQ line. The output IRQ level is formed as OR
> between all gpio inputs.
>
> Signed-off-by: Evgeny Voevodin
Reviewed-by: Peter Maydell
Not convinced it's worth putting
New IRQ gate consists of n_in input qdev gpio lines and one
output sysbus IRQ line. The output IRQ level is formed as OR
between all gpio inputs.
Signed-off-by: Evgeny Voevodin
---
hw/exynos4210.c | 32 +++--
hw/exynos4210.h |2 +-
hw/exynos4210_gic.c | 78 +++
Sorry, sent an old version. New version will be in next answer.
--
Kind regards,
Evgeny Voevodin,
Leading Software Engineer,
ASWG, Moscow R&D center, Samsung Electronics
e-mail: e.voevo...@samsung.com
New IRQ gate consists of n_in input qdev gpio lines and one
output sysbus IRQ line. The output IRQ level is formed as OR
between all gpio inputs.
Signed-off-by: Evgeny Voevodin
---
hw/exynos4210.c | 32 +++-
hw/exynos4210.h |2 +-
hw/exynos4210_gic.c | 79
