Signed-off-by: Stefan Brankovic <stefan.branko...@rt-rk.com>
---
tcg/i386/tcg-target.h | 2 +-
tcg/i386/tcg-target.inc.c | 10 ++++++++++
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index e825324..d20d08f 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -193,7 +193,7 @@ extern bool have_avx2;
#define TCG_TARGET_HAS_bitsel_vec 0
#define TCG_TARGET_HAS_cmpsel_vec -1
#define TCG_TARGET_HAS_vmrgh_vec 1
-#define TCG_TARGET_HAS_vmrgl_vec 0
+#define TCG_TARGET_HAS_vmrgl_vec 1
#define TCG_TARGET_deposit_i32_valid(ofs, len) \
(((ofs) == 0 && (len) == 8) || ((ofs) == 8 && (len) == 8) || \
diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c
index 31e1b2b..dc3cd65 100644
--- a/tcg/i386/tcg-target.inc.c
+++ b/tcg/i386/tcg-target.inc.c
@@ -2826,6 +2826,9 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_vmrgh_vec:
insn = punpckh_insn[vece];
goto gen_simd;
+ case INDEX_op_vmrgl_vec:
+ insn = punpckl_insn[vece];
+ goto gen_simd;
case INDEX_op_shlv_vec:
insn = shlv_insn[vece];
goto gen_simd;
@@ -3227,6 +3230,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode
op)
case INDEX_op_smax_vec:
case INDEX_op_umax_vec:
case INDEX_op_vmrgh_vec:
+ case INDEX_op_vmrgl_vec:
case INDEX_op_shlv_vec:
case INDEX_op_shrv_vec:
case INDEX_op_sarv_vec:
@@ -3327,6 +3331,8 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,
unsigned vece)
return vece <= MO_32;
case INDEX_op_vmrgh_vec:
return vece <= MO_32 ? -1 : 0;
+ case INDEX_op_vmrgl_vec:
+ return vece <= MO_32 ? -1 : 0;
default:
return 0;
@@ -3671,6 +3677,10 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type,
unsigned vece,
v2 = temp_tcgv_vec(arg_temp(a2));
expand_vec_vmrg(opc, type, vece, v0, v1, v2);
break;
+ case INDEX_op_vmrgl_vec:
+ v2 = temp_tcgv_vec(arg_temp(a2));
+ expand_vec_vmrg(opc, type, vece, v0, v1, v2);
+ break;
default:
break;
--
2.7.4
