Re: [Qemu-devel] [PATCH v4 14/21] target-mips: add AUI, LSA and PCREL instruction families

2014-11-13 Thread Leon Alrae
On 12/11/2014 21:07, Paolo Bonzini wrote: On 08/10/2014 12:55, Leon Alrae wrote: case OPC_LUI: -tcg_gen_movi_tl(cpu_gpr[rt], imm 16); -MIPS_DEBUG(lui %s, TARGET_FMT_lx, regnames[rt], uimm); +if (rs != 0 (ctx-insn_flags ISA_MIPS32R6)) { +/*

Re: [Qemu-devel] [PATCH v4 14/21] target-mips: add AUI, LSA and PCREL instruction families

2014-11-12 Thread Paolo Bonzini
On 08/10/2014 12:55, Leon Alrae wrote: case OPC_LUI: -tcg_gen_movi_tl(cpu_gpr[rt], imm 16); -MIPS_DEBUG(lui %s, TARGET_FMT_lx, regnames[rt], uimm); +if (rs != 0 (ctx-insn_flags ISA_MIPS32R6)) { +/* OPC_AUI */ +

Re: [Qemu-devel] [PATCH v4 14/21] target-mips: add AUI, LSA and PCREL instruction families

2014-10-14 Thread Leon Alrae
Hi Yongbok, On 13/10/2014 14:37, Yongbok Kim wrote: +OPC_PCREL= (0x3B 26), +}; + +/* PC-relative address computation / loads */ +#define MASK_OPC_PCREL_TOP2BITS(op) (MASK_OP_MAJOR(op) | (op (3 19))) +#define MASK_OPC_PCREL_TOP5BITS(op) (MASK_OP_MAJOR(op) | (op (0x1f 16)))

Re: [Qemu-devel] [PATCH v4 14/21] target-mips: add AUI, LSA and PCREL instruction families

2014-10-13 Thread Yongbok Kim
I have just few minor comments. Reviewed-by: Yongbok Kim yongbok@imgtec.com regards, Yongbok On 08/10/2014 11:55, Leon Alrae wrote: Signed-off-by: Leon Alrae leon.al...@imgtec.com --- v3: * use sextract32 instead of open coding the bit field extraction * replace _i64 with _tl in DAHI,

[Qemu-devel] [PATCH v4 14/21] target-mips: add AUI, LSA and PCREL instruction families

2014-10-08 Thread Leon Alrae
Signed-off-by: Leon Alrae leon.al...@imgtec.com --- v3: * use sextract32 instead of open coding the bit field extraction * replace _i64 with _tl in DAHI, DATI and DAUI * fix misleading LDPC comment --- disas/mips.c| 42 ++- target-mips/translate.c | 197