Loading an qemu pointer as an immediate happens often. E.g. - exit_tb $0x7fa8140013 + exit_tb $0x7f81ee0013 ... - : d2800260 mov x0, #0x13 - : f2b50280 movk x0, #0xa814, lsl #16 - : f2c00fe0 movk x0, #0x7f, lsl #32 + : 90ff1000 adrp x0, 0x7f81ee0000 + : 91004c00 add x0, x0, #0x13
Signed-off-by: Richard Henderson <r...@twiddle.net> --- tcg/aarch64/tcg-target.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index e50abcb..5691cc3 100644 --- a/tcg/aarch64/tcg-target.c +++ b/tcg/aarch64/tcg-target.c @@ -323,6 +323,10 @@ typedef enum { /* Conditional select instructions */ INSN_CSEL = 0x1a800000, INSN_CSINC = 0x1a800400, + + /* PC relative addressing instructions */ + INSN_ADR = 0x10000000, + INSN_ADRP = 0x90000000, } AArch64Insn; static inline enum aarch64_ldst_op_data @@ -510,6 +514,12 @@ static inline void tcg_fmt_Rd_uimm(TCGContext *s, AArch64Insn insn, tcg_out32(s, insn | sf << 31 | shift << (21 - 4) | half << 5 | rd); } +static inline void tcg_fmt_Rd_disp21(TCGContext *s, AArch64Insn insn, + TCGReg rd, tcg_target_long disp) +{ + tcg_out32(s, insn | (disp & 3) << 29 | (disp & 0x1ffffc) << (5 - 2) | rd); +} + static inline void tcg_out_ldst_9(TCGContext *s, enum aarch64_ldst_op_data op_data, enum aarch64_ldst_op_type op_type, @@ -561,7 +571,7 @@ static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, AArch64Insn insn; int i, wantinv, shift; tcg_target_long svalue = value; - tcg_target_long ivalue, imask; + tcg_target_long ivalue, imask, disp; /* For 32-bit values, discard potential garbage in value. For 64-bit values within [2**31, 2**32-1], we can create smaller sequences by @@ -593,6 +603,17 @@ static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, return; } + /* Look for host pointer values within 4G of the PC. This happens + often when loading pointers to QEMU's own data structures. */ + disp = (value >> 12) - ((intptr_t)s->code_ptr >> 12); + if (disp == sextract64(disp, 0, 21)) { + tcg_fmt_Rd_disp21(s, INSN_ADRP, rd, disp); + if (value & 0xfff) { + tcg_fmt_Rdn_aimm(s, INSN_ADDI, type, rd, rd, value & 0xfff); + } + return; + } + /* Would it take fewer insns to begin with MOVN? For the value and its inverse, count the number of 16-bit lanes that are 0. For the benefit of 32-bit quantities, compare the zero-extended normal value vs the -- 1.8.3.1