On Thu, Apr 28, 2016 at 06:56:05PM +0300, David Kiarie wrote:
[...]
> I think AMD IOMMU could be a benefit greatly from the Intel IOMMU
> cache implementation. There could be a few differences but I think
> much of the code could be reused. The thing is, AMD IOMMU spec doesn't
> mention anything
On Thu, Apr 28, 2016 at 11:49 AM, Peter Xu wrote:
> On Thu, Apr 28, 2016 at 10:36:19AM +0200, Jan Kiszka wrote:
>> On 2016-04-28 10:29, Peter Xu wrote:
>> > On Thu, Apr 28, 2016 at 09:26:01AM +0200, Jan Kiszka wrote:
>> >> On 2016-04-28 09:05, Peter Xu wrote:
>> >>> This patch
On Thu, Apr 28, 2016 at 10:36:19AM +0200, Jan Kiszka wrote:
> On 2016-04-28 10:29, Peter Xu wrote:
> > On Thu, Apr 28, 2016 at 09:26:01AM +0200, Jan Kiszka wrote:
> >> On 2016-04-28 09:05, Peter Xu wrote:
> >>> This patch introduces Intel VT-d IEC (Interrupt Entry Cache)
> >>> invalidation
On 2016-04-28 10:29, Peter Xu wrote:
> On Thu, Apr 28, 2016 at 09:26:01AM +0200, Jan Kiszka wrote:
>> On 2016-04-28 09:05, Peter Xu wrote:
>>> This patch introduces Intel VT-d IEC (Interrupt Entry Cache)
>>> invalidation notifier list. When vIOMMU receives IEC invalidate request,
>>> all the
On Thu, Apr 28, 2016 at 09:26:01AM +0200, Jan Kiszka wrote:
> On 2016-04-28 09:05, Peter Xu wrote:
> > This patch introduces Intel VT-d IEC (Interrupt Entry Cache)
> > invalidation notifier list. When vIOMMU receives IEC invalidate request,
> > all the registered units will be notified with
On 2016-04-28 09:05, Peter Xu wrote:
> This patch introduces Intel VT-d IEC (Interrupt Entry Cache)
> invalidation notifier list. When vIOMMU receives IEC invalidate request,
> all the registered units will be notified with specific invalidation
> requests.
This should be designed to be
This patch introduces Intel VT-d IEC (Interrupt Entry Cache)
invalidation notifier list. When vIOMMU receives IEC invalidate request,
all the registered units will be notified with specific invalidation
requests.
Signed-off-by: Peter Xu
---
hw/i386/intel_iommu.c | 56