From: Chen Gang <cheng...@emindsoft.com.cn>
normalize_roundpack_float32 is based on (u)int32_to_float32 function to
support float32 packing.
normalize_roundpack_float64 is the special case of roundAndPackFloat64.
Signed-off-by: Chen Gang <gang.chen.5...@gmail.com>
---
fpu/softfloat.c | 65 +++++++++++++++++++++++++++++++++++++++++++++++++
include/fpu/softfloat.h | 15 ++++++++++++
2 files changed, 80 insertions(+)
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index 166c48e..ecdfa7f 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -1516,6 +1516,16 @@ float64 uint64_to_float64(uint64_t a, float_status
*status)
return roundAndPackFloat64(0, exp - shiftcount, a, status);
}
+/*
+ * The mantissa contents the hide bit (60-bit), which is the special case of
+ * roundAndPackFloat64().
+ */
+float64 normalize_roundpack_float64(flag sign, int_fast16_t exp, uint64_t sig,
+ float_status *status)
+{
+ return roundAndPackFloat64(sign, exp - 1, sig << 3, status);
+}
+
/*----------------------------------------------------------------------------
| Returns the result of converting the 64-bit unsigned integer `a'
| to the quadruple-precision floating-point format. The conversion is
performed
@@ -7090,6 +7100,61 @@ float64 uint32_to_float64(uint32_t a, float_status
*status)
return int64_to_float64(a, status);
}
+/*
+ * The mantissa contents the hide bit, e.g. exp: 0x9e with sig: 1 means 1.0f.
+ *
+ * It references from int32_to_float32() and uint32_to_float32()
+ */
+float32 normalize_roundpack_float32(flag sign, int_fast16_t exp, uint32_t sig,
+ float_status *status)
+{
+ uint64_t absa = sig;
+ int8_t scount;
+
+ if (exp >= 0xff) {
+ return packFloat32(sign, 0xFF, 0);
+ } else if (exp <= 0) {
+ shift32RightJamming(sig, 0 - exp, &sig);
+ return packFloat32(sign, 0, sig);
+ }
+
+ if (sign) {
+ if (sig & 0x7FFFFFFF) {
+ return normalizeRoundAndPackFloat32(1, exp - 2, sig, status);
+ }
+ if (sig) {
+ return packFloat32(1, exp, 0);
+ } else {
+ return float32_zero;
+ }
+ }
+
+ if (!sig) {
+ return float32_zero;
+ }
+
+ scount = countLeadingZeros64(absa) - 40;
+ if (scount >= 0) {
+ exp -= 7 + scount + 2;
+ if (exp <= 0) {
+ return packFloat32(0, 0, absa);
+ }
+ return packFloat32(0, exp, absa << scount);
+ }
+
+ scount += 7;
+ exp -= scount + 2;
+ if (exp <= 0) {
+ return packFloat32(0, 0, absa);
+ }
+ if (scount < 0) {
+ shift64RightJamming(absa, 0 - scount, &absa);
+ } else {
+ absa <<= scount;
+ }
+ return roundAndPackFloat32(0, exp, absa, status);
+}
+
uint32_t float32_to_uint32(float32 a, float_status *status)
{
int64_t v;
diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
index c937062..d4246a1 100644
--- a/include/fpu/softfloat.h
+++ b/include/fpu/softfloat.h
@@ -409,6 +409,14 @@ int float32_is_signaling_nan( float32 );
float32 float32_maybe_silence_nan( float32 );
float32 float32_scalbn(float32, int, float_status *status);
+/*
+ * The mantissa contents the hide bit, e.g. exp: 0x9e with sig: 1 means 1.0f.
+ *
+ * It references from int32_to_float32() and uint32_to_float32()
+ */
+float32 normalize_roundpack_float32(flag sign, int_fast16_t exp, uint32_t sig,
+ float_status *status);
+
static inline float32 float32_abs(float32 a)
{
/* Note that abs does *not* handle NaN specially, nor does
@@ -521,6 +529,13 @@ int float64_is_signaling_nan( float64 );
float64 float64_maybe_silence_nan( float64 );
float64 float64_scalbn(float64, int, float_status *status);
+/*
+ * The mantissa contents the hide bit (60-bit), which is the special case of
+ * roundAndPackFloat64().
+ */
+float64 normalize_roundpack_float64(flag sign, int_fast16_t exp, uint64_t sig,
+ float_status *status);
+
static inline float64 float64_abs(float64 a)
{
/* Note that abs does *not* handle NaN specially, nor does
--
1.9.3
