Re: [Qemu-devel] [PATCH v6 4/4] target/mips: Optimize ILVR. MSA instructions

2019-04-17 Thread Mateja Marjanovic
On 16.4.19. 23:20, Aleksandar Markovic wrote: From: Mateja Marjanovic +void helper_msa_ilvr_b(CPUMIPSState *env, uint32_t wd, + uint32_t ws, uint32_t wt) +{ +wr_t *pwd = &(env->active_fpu.fpr[wd].wr); +wr_t *pws = &(env->active_fpu.fpr[ws].wr); +wr_t *pwt = &

Re: [Qemu-devel] [PATCH v6 4/4] target/mips: Optimize ILVR. MSA instructions

2019-04-16 Thread Aleksandar Markovic
> From: Mateja Marjanovic > >> > >> +void helper_msa_ilvr_b(CPUMIPSState *env, uint32_t wd, > >> + uint32_t ws, uint32_t wt) > >> +{ > >> +wr_t *pwd = &(env->active_fpu.fpr[wd].wr); > >> +wr_t *pws = &(env->active_fpu.fpr[ws].wr); > >> +wr_t *pwt = &(env->active_f

Re: [Qemu-devel] [PATCH v6 4/4] target/mips: Optimize ILVR. MSA instructions

2019-04-15 Thread Mateja Marjanovic
On 13.4.19. 18:05, Aleksandar Markovic wrote: On Thu, Apr 4, 2019 at 3:16 PM Mateja Marjanovic wrote: From: Mateja Marjanovic Optimized ILVR. instructions, using a hybrid Optimized -> Optimize approach. For byte data elements, use a helper with an unrolled loop (much better performance),

Re: [Qemu-devel] [PATCH v6 4/4] target/mips: Optimize ILVR. MSA instructions

2019-04-13 Thread Aleksandar Markovic
On Thu, Apr 4, 2019 at 3:16 PM Mateja Marjanovic wrote: > > From: Mateja Marjanovic > > Optimized ILVR. instructions, using a hybrid Optimized -> Optimize > approach. For byte data elements, use a helper with an > unrolled loop (much better performance), for halfword, (much better performance)

[Qemu-devel] [PATCH v6 4/4] target/mips: Optimize ILVR. MSA instructions

2019-04-04 Thread Mateja Marjanovic
From: Mateja Marjanovic Optimized ILVR. instructions, using a hybrid approach. For byte data elements, use a helper with an unrolled loop (much better performance), for halfword, word and doubleword data elements use directly tcg registers and logic performed on them. Performance measurement is