> From: Leon Alrae [mailto:leon.al...@imgtec.com]
> On 28/08/2015 10:08, Pavel Dovgaluk wrote:
> >> From: Aurelien Jarno [mailto:aurel...@aurel32.net]
> >> On 2015-08-13 14:12, Leon Alrae wrote:
> >>> On 10/07/2015 10:57, Pavel Dovgalyuk wrote:
> @@ -2364,14 +2363,12 @@ static void
On 28/08/2015 10:08, Pavel Dovgaluk wrote:
>> From: Aurelien Jarno [mailto:aurel...@aurel32.net]
>> On 2015-08-13 14:12, Leon Alrae wrote:
>>> On 10/07/2015 10:57, Pavel Dovgalyuk wrote:
@@ -2364,14 +2363,12 @@ static void gen_st_cond (DisasContext *ctx,
uint32_t opc, int rt,
#if
From: Aurelien Jarno [mailto:aurel...@aurel32.net]
On 2015-08-13 14:12, Leon Alrae wrote:
On 10/07/2015 10:57, Pavel Dovgalyuk wrote:
@@ -2364,14 +2363,12 @@ static void gen_st_cond (DisasContext *ctx,
uint32_t opc, int rt,
#if defined(TARGET_MIPS64)
case OPC_SCD:
On 2015-08-13 14:12, Leon Alrae wrote:
On 10/07/2015 10:57, Pavel Dovgalyuk wrote:
@@ -2364,14 +2363,12 @@ static void gen_st_cond (DisasContext *ctx,
uint32_t opc, int rt,
#if defined(TARGET_MIPS64)
case OPC_SCD:
case R6_OPC_SCD:
-save_cpu_state(ctx, 1);
On 10/07/2015 10:57, Pavel Dovgalyuk wrote:
@@ -2364,14 +2363,12 @@ static void gen_st_cond (DisasContext *ctx, uint32_t
opc, int rt,
#if defined(TARGET_MIPS64)
case OPC_SCD:
case R6_OPC_SCD:
-save_cpu_state(ctx, 1);
op_st_scd(t1, t0, rt, ctx);
opn =
This patch improves exception handling in MIPS.
Instructions generate several types of exceptions.
When exception is generated, it breaks the execution of the current translation
block. Implementation of the exceptions handling does not correctly
restore icount for the instruction which caused the
