On 27 April 2018 at 01:34, Michael Clark wrote:
> I wasn't sure whether I was going to send this series out before or after
> the 2.12 release and the remaining patches that need review depend on the
> earlier patches. The reason was so that patchew could digest the series i.e.
>
On Fri, Apr 27, 2018 at 12:35 PM, Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 04/26/2018 08:22 AM, Alistair Francis wrote:
> > On Wed, Apr 25, 2018 at 7:01 PM Michael Clark wrote:
> >> We can make a PR for the first 9 patches as they are already reviewed,
> >>
On 04/26/2018 08:22 AM, Alistair Francis wrote:
> On Wed, Apr 25, 2018 at 7:01 PM Michael Clark wrote:
>> We can make a PR for the first 9 patches as they are already reviewed,
>> however, the with this series is to gather review for the new baseline we
>> have in the riscv repo.
On Fri, Apr 27, 2018 at 6:22 AM, Alistair Francis
wrote:
> On Wed, Apr 25, 2018 at 7:01 PM Michael Clark wrote:
>
> > One last quick note.
>
> > We are tracking RISC-V QEMU issues in the riscv.org repo:
>
> > - https://github.com/riscv/riscv-qemu/issues
>
On Wed, Apr 25, 2018 at 7:01 PM Michael Clark wrote:
> One last quick note.
> We are tracking RISC-V QEMU issues in the riscv.org repo:
> - https://github.com/riscv/riscv-qemu/issues
> We have tagged issues that are resolved in the 'qemu-2.13-for-upstream'
> branch (this
One last quick note.
We are tracking RISC-V QEMU issues in the riscv.org repo:
- https://github.com/riscv/riscv-qemu/issues
We have tagged issues that are resolved in the 'qemu-2.13-for-upstream'
branch (this branch can be rebased if we re-spin)
-
Hi All,
As a first-time QEMU contributor, it was quite a challenge to get an entire
port accepted upstream into QEMU. As folk who have followed the progress of
the port will know; at moments my nerves got the better of me as we
approached soft-freeze. In any case, I'd like to thank everyone who
This is a series of bug fixes, specification conformance
fixes and CPU feature modularily updates to allow more
precise modelling of the SiFive U Series CPUs (multi-core
application processors with MMU, Supervisor and User modes)
and SiFive E Series CPUs (embedded microcontroller cores
without MMU