From: Yongbok Kim <yongbok....@mips.com>
Add emulation of nanoMIPS 16-bit branch instructions.
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Yongbok Kim <yongbok....@mips.com>
Signed-off-by: Aleksandar Markovic <amarko...@wavecomp.com>
Signed-off-by: Stefan Markovic <smarko...@wavecomp.com>
---
target/mips/translate.c | 36 ++++++++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 85ecf23..0b9936f 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -16799,14 +16799,50 @@ static int decode_nanomips_opc(CPUMIPSState *env,
DisasContext *ctx)
case NM_SWGP16:
break;
case NM_BC16:
+ gen_compute_branch(ctx, OPC_BEQ, 2, 0, 0,
+ (sextract32(ctx->opcode, 0, 1) << 10) |
+ (extract32(ctx->opcode, 1, 9) << 1), 0);
break;
case NM_BALC16:
+ gen_compute_branch(ctx, OPC_BGEZAL, 2, 0, 0,
+ (sextract32(ctx->opcode, 0, 1) << 10) |
+ (extract32(ctx->opcode, 1, 9) << 1), 0);
break;
case NM_BEQZC16:
+ gen_compute_branch(ctx, OPC_BEQ, 2, rt, 0,
+ (sextract32(ctx->opcode, 0, 1) << 7) |
+ (extract32(ctx->opcode, 1, 6) << 1), 0);
break;
case NM_BNEZC16:
+ gen_compute_branch(ctx, OPC_BNE, 2, rt, 0,
+ (sextract32(ctx->opcode, 0, 1) << 7) |
+ (extract32(ctx->opcode, 1, 6) << 1), 0);
break;
case NM_P16_BR:
+ switch (ctx->opcode & 0xf) {
+ case 0:
+ /* P16.JRC */
+ switch (extract32(ctx->opcode, 4, 1)) {
+ case NM_JRC:
+ gen_compute_branch(ctx, OPC_JR, 2,
+ extract32(ctx->opcode, 5, 5), 0, 0, 0);
+ break;
+ case NM_JALRC16:
+ gen_compute_branch(ctx, OPC_JALR, 2,
+ extract32(ctx->opcode, 5, 5), 31, 0, 0);
+ break;
+ }
+ break;
+ default:
+ {
+ /* P16.BRI */
+ uint32_t opc = extract32(ctx->opcode, 4, 3) <
+ extract32(ctx->opcode, 7, 3) ? OPC_BEQ :
OPC_BNE;
+ gen_compute_branch(ctx, opc, 2, rs, rt,
+ extract32(ctx->opcode, 0, 4) << 1, 0);
+ }
+ break;
+ }
break;
case NM_P16_SR:
break;
--
2.7.4
