Re: [Qemu-devel] [PATCHv3 7/7] spapr: Improved placement of PCI host bridges in guest memory map

On Fri, Oct 14, 2016 at 09:25:58AM +0200, Laurent Vivier wrote: > On 14/10/2016 01:29, David Gibson wrote: > > From 98f07c09c6d72218800d6cfbf44b973a88ece2aa Mon Sep 17 00:00:00 2001 > > From: David Gibson > > Date: Fri, 14 Oct 2016 10:21:00 +1100 > > Subject: [PATCH]

Re: [Qemu-devel] [PATCHv3 7/7] spapr: Improved placement of PCI host bridges in guest memory map

On 14/10/2016 01:29, David Gibson wrote: > From 98f07c09c6d72218800d6cfbf44b973a88ece2aa Mon Sep 17 00:00:00 2001 > From: David Gibson > Date: Fri, 14 Oct 2016 10:21:00 +1100 > Subject: [PATCH] spapr: Improved placement of PCI host bridges in guest memory > map > >

Re: [Qemu-devel] [PATCHv3 7/7] spapr: Improved placement of PCI host bridges in guest memory map

On Thu, Oct 13, 2016 at 10:40:32AM +0200, Laurent Vivier wrote: > > > On 13/10/2016 01:57, David Gibson wrote: > > Currently, the MMIO space for accessing PCI on pseries guests begins at > > 1 TiB in guest address space. Each PCI host bridge (PHB) has a 64 GiB > > chunk of address space in

Re: [Qemu-devel] [PATCHv3 7/7] spapr: Improved placement of PCI host bridges in guest memory map

On 13/10/2016 01:57, David Gibson wrote: > Currently, the MMIO space for accessing PCI on pseries guests begins at > 1 TiB in guest address space. Each PCI host bridge (PHB) has a 64 GiB > chunk of address space in which it places its outbound PIO and 32-bit and > 64-bit MMIO windows. > > This

[Qemu-devel] [PATCHv3 7/7] spapr: Improved placement of PCI host bridges in guest memory map

Currently, the MMIO space for accessing PCI on pseries guests begins at 1 TiB in guest address space. Each PCI host bridge (PHB) has a 64 GiB chunk of address space in which it places its outbound PIO and 32-bit and 64-bit MMIO windows. This scheme as several problems: - It limits guest RAM to