Currently PCI memory (aka MMIO) space is accessed via a set of readb/writeb
style accessors. This is what we want for accessing discrete registers of
a certain size. However, there are a few cases where we instead need a
"bag of bytes" style streaming interface to PCI MMIO space. This can be
either for streaming data style registers or when there's actual memory
rather than registers in PCI space, for example frame buffers or ivshmem.
This patch adds backend callbacks, and libqos wrappers for this type of
byte address order preserving accesses.
Signed-off-by: David Gibson <da...@gibson.dropbear.id.au>
Reviewed-by: Laurent Vivier <lviv...@redhat.com>
Reviewed-by: Greg Kurz <gr...@kaod.org>
---
tests/libqos/pci-pc.c | 14 ++++++++++++++
tests/libqos/pci-spapr.c | 17 +++++++++++++++++
tests/libqos/pci.c | 16 ++++++++++++++++
tests/libqos/pci.h | 6 ++++++
4 files changed, 53 insertions(+)
diff --git a/tests/libqos/pci-pc.c b/tests/libqos/pci-pc.c
index d0eb84a..84aee25 100644
--- a/tests/libqos/pci-pc.c
+++ b/tests/libqos/pci-pc.c
@@ -87,6 +87,17 @@ static void qpci_pc_mmio_writel(QPCIBus *bus, uint32_t addr,
uint32_t val)
writel(addr, val);
}
+static void qpci_pc_memread(QPCIBus *bus, uint32_t addr, void *buf, size_t len)
+{
+ memread(addr, buf, len);
+}
+
+static void qpci_pc_memwrite(QPCIBus *bus, uint32_t addr,
+ const void *buf, size_t len)
+{
+ memwrite(addr, buf, len);
+}
+
static uint8_t qpci_pc_config_readb(QPCIBus *bus, int devfn, uint8_t offset)
{
outl(0xcf8, (1U << 31) | (devfn << 8) | offset);
@@ -145,6 +156,9 @@ QPCIBus *qpci_init_pc(QGuestAllocator *alloc)
ret->bus.mmio_writew = qpci_pc_mmio_writew;
ret->bus.mmio_writel = qpci_pc_mmio_writel;
+ ret->bus.memread = qpci_pc_memread;
+ ret->bus.memwrite = qpci_pc_memwrite;
+
ret->bus.config_readb = qpci_pc_config_readb;
ret->bus.config_readw = qpci_pc_config_readw;
ret->bus.config_readl = qpci_pc_config_readl;
diff --git a/tests/libqos/pci-spapr.c b/tests/libqos/pci-spapr.c
index 70a24b5..ad12c2e 100644
--- a/tests/libqos/pci-spapr.c
+++ b/tests/libqos/pci-spapr.c
@@ -114,6 +114,20 @@ static void qpci_spapr_mmio32_writel(QPCIBus *bus,
uint32_t addr, uint32_t val)
writel(s->mmio32_cpu_base + addr, bswap32(val));
}
+static void qpci_spapr_memread(QPCIBus *bus, uint32_t addr,
+ void *buf, size_t len)
+{
+ QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
+ memread(s->mmio32_cpu_base + addr, buf, len);
+}
+
+static void qpci_spapr_memwrite(QPCIBus *bus, uint32_t addr,
+ const void *buf, size_t len)
+{
+ QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
+ memwrite(s->mmio32_cpu_base + addr, buf, len);
+}
+
static uint8_t qpci_spapr_config_readb(QPCIBus *bus, int devfn, uint8_t offset)
{
QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
@@ -188,6 +202,9 @@ QPCIBus *qpci_init_spapr(QGuestAllocator *alloc)
ret->bus.mmio_writew = qpci_spapr_mmio32_writew;
ret->bus.mmio_writel = qpci_spapr_mmio32_writel;
+ ret->bus.memread = qpci_spapr_memread;
+ ret->bus.memwrite = qpci_spapr_memwrite;
+
ret->bus.config_readb = qpci_spapr_config_readb;
ret->bus.config_readw = qpci_spapr_config_readw;
ret->bus.config_readl = qpci_spapr_config_readl;
diff --git a/tests/libqos/pci.c b/tests/libqos/pci.c
index 98a2e56..146b063 100644
--- a/tests/libqos/pci.c
+++ b/tests/libqos/pci.c
@@ -289,6 +289,22 @@ void qpci_io_writel(QPCIDevice *dev, void *data, uint32_t
value)
}
}
+void qpci_memread(QPCIDevice *dev, void *data, void *buf, size_t len)
+{
+ uintptr_t addr = (uintptr_t)data;
+
+ g_assert(addr >= QPCI_PIO_LIMIT);
+ dev->bus->memread(dev->bus, addr, buf, len);
+}
+
+void qpci_memwrite(QPCIDevice *dev, void *data, const void *buf, size_t len)
+{
+ uintptr_t addr = (uintptr_t)data;
+
+ g_assert(addr >= QPCI_PIO_LIMIT);
+ dev->bus->memwrite(dev->bus, addr, buf, len);
+}
+
void *qpci_iomap(QPCIDevice *dev, int barno, uint64_t *sizeptr)
{
QPCIBus *bus = dev->bus;
diff --git a/tests/libqos/pci.h b/tests/libqos/pci.h
index b6f855e..2b08362 100644
--- a/tests/libqos/pci.h
+++ b/tests/libqos/pci.h
@@ -39,6 +39,9 @@ struct QPCIBus {
void (*mmio_writew)(QPCIBus *bus, uint32_t addr, uint16_t value);
void (*mmio_writel)(QPCIBus *bus, uint32_t addr, uint32_t value);
+ void (*memread)(QPCIBus *bus, uint32_t addr, void *buf, size_t len);
+ void (*memwrite)(QPCIBus *bus, uint32_t addr, const void *buf, size_t len);
+
uint8_t (*config_readb)(QPCIBus *bus, int devfn, uint8_t offset);
uint16_t (*config_readw)(QPCIBus *bus, int devfn, uint8_t offset);
uint32_t (*config_readl)(QPCIBus *bus, int devfn, uint8_t offset);
@@ -92,6 +95,9 @@ void qpci_io_writeb(QPCIDevice *dev, void *data, uint8_t
value);
void qpci_io_writew(QPCIDevice *dev, void *data, uint16_t value);
void qpci_io_writel(QPCIDevice *dev, void *data, uint32_t value);
+void qpci_memread(QPCIDevice *bus, void *data, void *buf, size_t len);
+void qpci_memwrite(QPCIDevice *bus, void *data, const void *buf, size_t len);
+
void *qpci_iomap(QPCIDevice *dev, int barno, uint64_t *sizeptr);
void qpci_iounmap(QPCIDevice *dev, void *data);
void *qpci_legacy_iomap(QPCIDevice *dev, uint16_t addr);
--
2.7.4
