Hello Peter, have you had a chance to look at this?
On Mon, Mar 28, 2016 at 3:15 PM, Aurelio Remonda
wrote:
>>> #define NUM_IRQ_LINES 64
>>> +#define LM3S811EVB_DEFAULT_DC0 0x1f00 /* Default value for dc0
>>> sram_size half */
>>> +#define LM3S6965EVB_DEFAULT_DC0 0xff00 /* Default value
On 28 March 2016 at 19:15, Aurelio Remonda
wrote:
>>> #define NUM_IRQ_LINES 64
>>> +#define LM3S811EVB_DEFAULT_DC0 0x1f00 /* Default value for dc0
>>> sram_size half */
>>> +#define LM3S6965EVB_DEFAULT_DC0 0xff00 /* Default value for dc0
>>> sram_size half */
>>
>> These don't seem to b
Ok, but I explained my decisions on a the mail dated 03/28, responding
on your mail dated 03/23 maybe you missed that mail.
Thanks!
On 14 April 2016 at 13:21, Aurelio Remonda
wrote:
> Hello Peter, have you had a chance to look at this?
I made review comments in my previous mail on this patch, which means
it's now back to you to update the patch and resend.
thanks
-- PMM
>> #define NUM_IRQ_LINES 64
>> +#define LM3S811EVB_DEFAULT_DC0 0x1f00 /* Default value for dc0
>> sram_size half */
>> +#define LM3S6965EVB_DEFAULT_DC0 0xff00 /* Default value for dc0
>> sram_size half */
>
> These don't seem to be the same as the default values we had previously ?
I th
On 21 March 2016 at 18:42, Aurelio Remonda
wrote:
> This patch adds the memory flag to both stellaris LM3S811EVB
> and LM3S6965EVB.
>
> The hardcoded dc0 values for both boards still exists but now the higher 16
> bits
> are calculated based on ram_size which could be either user-given or the
>
This patch adds the memory flag to both stellaris LM3S811EVB
and LM3S6965EVB.
The hardcoded dc0 values for both boards still exists but now the higher 16 bits
are calculated based on ram_size which could be either user-given or the default
one. Then the sram_size is calculated as usual, flash_size
