Re: [Qemu-devel] [PULL 09/11] tcg-aarch64: Use 32-bit loads for qemu_ld_i32

2014-09-25 Thread Claudio Fontana
On 24.09.2014 17:19, Richard Henderson wrote: > On 09/24/2014 01:20 AM, Claudio Fontana wrote: >>> @@ -1118,7 +1119,8 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, >>> TCGMemOp memop, >>> tcg_out_ldst_r(s, I3312_LDRB, data_r, addr_r, off_r); >>> break; >>> case MO_SB:

Re: [Qemu-devel] [PULL 09/11] tcg-aarch64: Use 32-bit loads for qemu_ld_i32

2014-09-24 Thread Richard Henderson
On 09/24/2014 01:20 AM, Claudio Fontana wrote: >> @@ -1118,7 +1119,8 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, >> TCGMemOp memop, >> tcg_out_ldst_r(s, I3312_LDRB, data_r, addr_r, off_r); >> break; >> case MO_SB: >> -tcg_out_ldst_r(s, I3312_LDRSBX, data_r,

Re: [Qemu-devel] [PULL 09/11] tcg-aarch64: Use 32-bit loads for qemu_ld_i32

2014-09-24 Thread Claudio Fontana
As I mentioned before, I just have one nit with this, functionally it is fine (and I tested it with multiple targets, so you can add my Tested-by: Claudio Fontana I describe my nit below: On 22.09.2014 22:57, Richard Henderson wrote: > The "old" qemu_ld opcode did not specify the size of the r

[Qemu-devel] [PULL 09/11] tcg-aarch64: Use 32-bit loads for qemu_ld_i32

2014-09-22 Thread Richard Henderson
The "old" qemu_ld opcode did not specify the size of the result, and so we had to assume full register width. With the new opcodes, we can narrow the result. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 29 - tcg/tcg-be-ldst.h| 1 + 2 file