From: "Maciej W. Rozycki" <ma...@codesourcery.com>
Make microMIPS FP branches respect CP0.Status.CU1 and trap with a
Coprocessor Unusable exception if COP1 has been disabled; also trap if
no FPU is present at all.
Standard MIPS FP instruction encodings have a more regular structure and
branches are covered with a single umbrella along other instructions.
This is not the case with the microMIPS encoding, this case has to be
taken care of explicitly here. Code to do so has been copied from the
standard MIPS code handler for OPC_CP1, in `decode_opc'.
Problems arising from this bug will generally only show up on user
context switches in operating systems making use of lazy FP context
switches, such as Linux. It will also more readily trigger if software
FPU emulation is used, either implicitly on a non-float CPU, or forced
on a hard-float CPU such as with the "nofpu" Linux kernel command line
argument.
The problem may have been easily missed because we have no hard-float
microMIPS CPU configuration present; in fact we have no microMIPS CPU
configuration of any kind present.
Signed-off-by: Maciej W. Rozycki <ma...@codesourcery.com>
Reviewed-by: Leon Alrae <leon.al...@imgtec.com>
Signed-off-by: Leon Alrae <leon.al...@imgtec.com>
---
target-mips/translate.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 2117ce8..d6722e1 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -13613,8 +13613,13 @@ static void decode_micromips32_opc (CPUMIPSState *env,
DisasContext *ctx,
check_insn(ctx, ASE_MIPS3D);
/* Fall through */
do_cp1branch:
- gen_compute_branch1(ctx, mips32_op,
- (ctx->opcode >> 18) & 0x7, imm << 1);
+ if (env->CP0_Config1 & (1 << CP0C1_FP)) {
+ check_cp1_enabled(ctx);
+ gen_compute_branch1(ctx, mips32_op,
+ (ctx->opcode >> 18) & 0x7, imm << 1);
+ } else {
+ generate_exception_err(ctx, EXCP_CpU, 1);
+ }
break;
case BPOSGE64:
case BPOSGE32:
--
2.1.0
