From: Cédric Le Goater <c...@kaod.org>
This extracts from the PvChip realize routine the part creating the
cores. On Power9, we will need to create the cores after the Xive
interrupt controller is created.
Signed-off-by: Cédric Le Goater <c...@kaod.org>
Signed-off-by: David Gibson <da...@gibson.dropbear.id.au>
---
hw/ppc/pnv.c | 32 ++++++++++++++++++++++----------
1 file changed, 22 insertions(+), 10 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 0b9508d94d..0d2b79f798 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -849,9 +849,8 @@ static void pnv_chip_icp_realize(PnvChip *chip, Error
**errp)
}
}
-static void pnv_chip_realize(DeviceState *dev, Error **errp)
+static void pnv_chip_core_realize(PnvChip *chip, Error **errp)
{
- PnvChip *chip = PNV_CHIP(dev);
Error *error = NULL;
PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
const char *typename = pnv_chip_core_typename(chip);
@@ -863,14 +862,6 @@ static void pnv_chip_realize(DeviceState *dev, Error
**errp)
return;
}
- /* XSCOM bridge */
- pnv_xscom_realize(chip, &error);
- if (error) {
- error_propagate(errp, error);
- return;
- }
- sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip));
-
/* Cores */
pnv_chip_core_sanitize(chip, &error);
if (error) {
@@ -918,6 +909,27 @@ static void pnv_chip_realize(DeviceState *dev, Error
**errp)
&PNV_CORE(pnv_core)->xscom_regs);
i++;
}
+}
+
+static void pnv_chip_realize(DeviceState *dev, Error **errp)
+{
+ PnvChip *chip = PNV_CHIP(dev);
+ Error *error = NULL;
+
+ /* XSCOM bridge */
+ pnv_xscom_realize(chip, &error);
+ if (error) {
+ error_propagate(errp, error);
+ return;
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip));
+
+ /* Cores */
+ pnv_chip_core_realize(chip, &error);
+ if (error) {
+ error_propagate(errp, error);
+ return;
+ }
/* Create LPC controller */
object_property_set_bool(OBJECT(&chip->lpc), true, "realized",
--
2.17.1
