> On Jul 4, 2019, at 08:45, Philippe Mathieu-Daudé wrote:
>
> Cc'ing PPC/taihu_405ep and ARM/Digic4 maintainers.
>
> On 7/3/19 6:36 PM, Philippe Mathieu-Daudé wrote:
>> On 7/3/19 6:20 PM, Stephen Checkoway wrote:
On Jul 3, 2019, at 12:02, Philippe Mathieu-Daudé wrote:
On 7/3/19
Cc'ing PPC/taihu_405ep and ARM/Digic4 maintainers.
On 7/3/19 6:36 PM, Philippe Mathieu-Daudé wrote:
> On 7/3/19 6:20 PM, Stephen Checkoway wrote:
>>> On Jul 3, 2019, at 12:02, Philippe Mathieu-Daudé wrote:
>>> On 7/3/19 5:52 PM, Stephen Checkoway wrote:
> On Jul 1, 2019, at 20:59,
On 7/3/19 6:20 PM, Stephen Checkoway wrote:
>> On Jul 3, 2019, at 12:02, Philippe Mathieu-Daudé wrote:
>> On 7/3/19 5:52 PM, Stephen Checkoway wrote:
>>>
>>>
On Jul 1, 2019, at 20:59, Philippe Mathieu-Daudé wrote:
Parallel NOR flashes are limited to 16-bit bus accesses.
>>>
>>> I
On 7/3/19 5:52 PM, Stephen Checkoway wrote:
>
>
>> On Jul 1, 2019, at 20:59, Philippe Mathieu-Daudé wrote:
>>
>> Parallel NOR flashes are limited to 16-bit bus accesses.
>
> I don't think this is correct. The CFI spec defines an x32 interface for
> parallel NOR. CFI addresses 0x28 and 0x29
> On Jul 3, 2019, at 12:02, Philippe Mathieu-Daudé wrote:
>
> On 7/3/19 5:52 PM, Stephen Checkoway wrote:
>>
>>
>>> On Jul 1, 2019, at 20:59, Philippe Mathieu-Daudé wrote:
>>>
>>> Parallel NOR flashes are limited to 16-bit bus accesses.
>>
>> I don't think this is correct. The CFI spec
> On Jul 1, 2019, at 20:59, Philippe Mathieu-Daudé wrote:
>
> Parallel NOR flashes are limited to 16-bit bus accesses.
I don't think this is correct. The CFI spec defines an x32 interface for
parallel NOR. CFI addresses 0x28 and 0x29 specify the interface and value 3 is
x32 and value 5 is
Parallel NOR flashes are limited to 16-bit bus accesses.
Remove the 32-bit dead code.
Reviewed-by: Alistair Francis
Message-Id: <20190627202719.17739-29-phi...@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé
---
hw/block/pflash_cfi02.c | 5 +
1 file changed, 1 insertion(+), 4
