From: Babu Moger <babu.mo...@amd.com>
Initialize pre-determined cache information for EPYC processors.
Signed-off-by: Babu Moger <babu.mo...@amd.com>
Tested-by: Geoffrey McRae <ge...@hostfission.com>
Message-Id: <20180510204148.11687-5-babu.mo...@amd.com>
Signed-off-by: Eduardo Habkost <ehabk...@redhat.com>
---
target/i386/cpu.c | 52 ++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 52 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 55685ed19d..174a8f434b 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1109,6 +1109,56 @@ struct X86CPUDefinition {
CPUCaches *cache_info;
};
+static CPUCaches epyc_cache_info = {
+ .l1d_cache = {
+ .type = DCACHE,
+ .level = 1,
+ .size = 32 * KiB,
+ .line_size = 64,
+ .associativity = 8,
+ .partitions = 1,
+ .sets = 64,
+ .lines_per_tag = 1,
+ .self_init = 1,
+ .no_invd_sharing = true,
+ },
+ .l1i_cache = {
+ .type = ICACHE,
+ .level = 1,
+ .size = 64 * KiB,
+ .line_size = 64,
+ .associativity = 4,
+ .partitions = 1,
+ .sets = 256,
+ .lines_per_tag = 1,
+ .self_init = 1,
+ .no_invd_sharing = true,
+ },
+ .l2_cache = {
+ .type = UNIFIED_CACHE,
+ .level = 2,
+ .size = 512 * KiB,
+ .line_size = 64,
+ .associativity = 8,
+ .partitions = 1,
+ .sets = 1024,
+ .lines_per_tag = 1,
+ },
+ .l3_cache = {
+ .type = UNIFIED_CACHE,
+ .level = 3,
+ .size = 8 * MiB,
+ .line_size = 64,
+ .associativity = 16,
+ .partitions = 1,
+ .sets = 8192,
+ .lines_per_tag = 1,
+ .self_init = true,
+ .inclusive = true,
+ .complex_indexing = true,
+ },
+};
+
static X86CPUDefinition builtin_x86_defs[] = {
{
.name = "qemu64",
@@ -2345,6 +2395,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_6_EAX_ARAT,
.xlevel = 0x8000000A,
.model_id = "AMD EPYC Processor",
+ .cache_info = &epyc_cache_info,
},
{
.name = "EPYC-IBPB",
@@ -2391,6 +2442,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_6_EAX_ARAT,
.xlevel = 0x8000000A,
.model_id = "AMD EPYC Processor (with IBPB)",
+ .cache_info = &epyc_cache_info,
},
};
--
2.14.3
