Re: [Qemu-devel] [PULL v2 12/12] target/mips: Introduce 32 R5900 multimedia registers

2020-12-12 Thread Fredrik Noring
On Sat, Nov 14, 2020 at 07:23:10PM +0100, Philippe Mathieu-Daudé wrote: > Hi Fredrik and Aleksandar, > > On Fri, Jan 18, 2019 at 6:10 PM Aleksandar Markovic > wrote: > > > > From: Fredrik Noring > > > > The 32 R5900 128-bit registers are split into two 64-bit halves: > > the lower halves are the

Re: [Qemu-devel] [PULL v2 12/12] target/mips: Introduce 32 R5900 multimedia registers

2020-11-14 Thread Philippe Mathieu-Daudé
Hi Fredrik and Aleksandar, On Fri, Jan 18, 2019 at 6:10 PM Aleksandar Markovic wrote: > > From: Fredrik Noring > > The 32 R5900 128-bit registers are split into two 64-bit halves: > the lower halves are the GPRs and the upper halves are accessible > by the R5900-specific multimedia instructions.

[Qemu-devel] [PULL v2 12/12] target/mips: Introduce 32 R5900 multimedia registers

2019-01-18 Thread Aleksandar Markovic
From: Fredrik Noring The 32 R5900 128-bit registers are split into two 64-bit halves: the lower halves are the GPRs and the upper halves are accessible by the R5900-specific multimedia instructions. Reviewed-by: Aleksandar Markovic Signed-off-by: Fredrik Noring Signed-off-by: Aleksandar Markov