as anyone who did it knows, describing memory mapped peripherals is tedious. as
far as I know, qemu support ends at defining memory regions and implementing
the read/write callbacks for all accesses in this region.
while implementing several Cortex-M devices (currently STM32F103, F107, F407,
F4
On Wed, Jul 8, 2015 at 1:14 PM, Liviu Ionescu wrote:
> as anyone who did it knows, describing memory mapped peripherals is tedious.
> as far as I know, qemu support ends at defining memory regions and
> implementing the read/write callbacks for all accesses in this region.
>
> while implementing
> On 08 Jul 2015, at 23:22, Peter Crosthwaite
> wrote:
>
> I have an RFC on list for something very similar, if you want to weigh
> in or find it useful, let me know! This is a real problem.
>
> https://lists.nongnu.org/archive/html/qemu-devel/2015-04/msg03612.html
ok, so the problem is real.
On Wed, Jul 8, 2015 at 6:50 PM, Liviu Ionescu wrote:
>
>> On 08 Jul 2015, at 23:22, Peter Crosthwaite
>> wrote:
>>
>> I have an RFC on list for something very similar, if you want to weigh
>> in or find it useful, let me know! This is a real problem.
>>
>> https://lists.nongnu.org/archive/html/q
> On 08 Jul 2015, at 23:22, Peter Crosthwaite
> wrote:
>
> ... an RFC on list for something very similar, if you want to weigh
> in or find it useful, let me know!
yes, if you are not in a hurry to commit your patches, I guess together we can
find a suitable solution.
as already mentioned, m
