Re: [Qemu-devel] [RFC 0/1] riscv: Add full-system emulation support for the RISC-V Instruction Set Architecture (RV64G)

On 02/18/2016 05:02 PM, Sagar Karandikar wrote: > Some notes/questions: > - This provides support only for the 64-bit version of the ISA and full > system > emulation (no user-mode) > - This currently applies to the 2.5.0 release version. I will bump the > underlying codebase, split this

Re: [Qemu-devel] [RFC 0/1] riscv: Add full-system emulation support for the RISC-V Instruction Set Architecture (RV64G)

On Thu, Feb 18, 2016 at 05:02:04PM -0800, Sagar Karandikar wrote: > With this RFC, I mainly wanted to get input on the overall design of the > target > implementation, as well as see if any regular contributors would be > interested > in co-mentoring RISC-V related projects for QEMU's Google

Re: [Qemu-devel] [RFC 0/1] riscv: Add full-system emulation support for the RISC-V Instruction Set Architecture (RV64G)

On 19 February 2016 at 01:02, Sagar Karandikar wrote: > The patch in this RFC adds support for the RISC-V ISA [1] as a target. It has > been tested booting Linux and FreeBSD, passes the RISC-V assembly test suite, > and has had the riscv-torture tester running on it for

Re: [Qemu-devel] [RFC 0/1] riscv: Add full-system emulation support for the RISC-V Instruction Set Architecture (RV64G)

On Thu, Feb 18, 2016 at 05:02:04PM -0800, Sagar Karandikar wrote: > - The devices in hw/riscv/htif are intended to mimic the experimental devices > that we use with our RISC-V test chips. These will be removed and replaced > with "real" devices once there is better software support in the >

[Qemu-devel] [RFC 0/1] riscv: Add full-system emulation support for the RISC-V Instruction Set Architecture (RV64G)

The patch in this RFC adds support for the RISC-V ISA [1] as a target. It has been tested booting Linux and FreeBSD, passes the RISC-V assembly test suite, and has had the riscv-torture tester running on it for a couple of weeks now without any issues arising. With this RFC, I mainly wanted to