Encoding of page sizes on 64-bit hash MMUs for Power is rather arcane,
involving control bits in both the SLB and HPTE. At present we
support a few of the options, but far fewer than real hardware.
We're able to get away with that in practice, because guests use a
device tree property to determine which page sizes are available and
we are setting that to match. However, the fact that the actual code
doesn't necessarily what we put into the table of available page sizes
is another ugliness.
This series makes a number of cleanups to the page size handling. The
upshot is that afterwards the softmmu code operates off the same page
size encoding table that is advertised to the guests, ensuring that
they will be in sync.
Finally, we extend the table of allowed sizes for POWER7 and POWER8 to
include the options allowed in hardware (including MPSS). We can fix
other hash MMU based CPUs in future if anyone cares enough.
Once reviewed, I plan to include this in my ppc-for-2.6 tree.
David Gibson (9):
target-ppc: Remove unused kvmppc_read_segment_page_sizes() stub
target-ppc: Convert mmu-hash{32,64}.[ch] from CPUPPCState to
PowerPCCPU
target-ppc: Rework SLB page size lookup
target-ppc: Use actual page size encodings from HPTE
target-ppc: Remove unused mmu models from ppc_tlb_invalidate_one
target-ppc: Split 44x tlbiva from ppc_tlb_invalidate_one()
target-ppc: Add new TLB invalidate by HPTE call for hash64 MMUs
target-ppc: Helper to determine page size information from hpte alone
target-ppc: Allow more page sizes for POWER7 & POWER8 in TCG
hw/ppc/spapr_hcall.c | 102 ++++------------
target-ppc/helper.h | 1 +
target-ppc/kvm.c | 2 +-
target-ppc/kvm_ppc.h | 5 -
target-ppc/mmu-hash32.c | 68 ++++++-----
target-ppc/mmu-hash32.h | 30 ++---
target-ppc/mmu-hash64.c | 280 +++++++++++++++++++++++++++++++++-----------
target-ppc/mmu-hash64.h | 29 +++--
target-ppc/mmu_helper.c | 47 +++-----
target-ppc/translate.c | 2 +-
target-ppc/translate_init.c | 32 +++++
11 files changed, 364 insertions(+), 234 deletions(-)
--
2.5.0
