On 06/27/2016 01:41 PM, Emilio G. Cota wrote:
Supporting 64-bit hosts on 32-bit guests has the problem of non-atomicity
of 64-bit accesses, however.
It does. It would be possible to do something with armv7 and i686 hosts, as
64-bit atomic ops exist, but it's probably not worth the effort.
A
On Mon, Jun 27, 2016 at 13:07:42 -0700, Richard Henderson wrote:
> On 06/27/2016 12:01 PM, Emilio G. Cota wrote:
> >This set of locks will allow us to correctly emulate cmpxchg16
> >in a parallel TCG. The key observation is that no architecture
> >supports 16-byte regular atomic load/stores; only "
On 06/27/2016 12:01 PM, Emilio G. Cota wrote:
This set of locks will allow us to correctly emulate cmpxchg16
in a parallel TCG. The key observation is that no architecture
supports 16-byte regular atomic load/stores; only "locked" accesses
(e.g. via cmpxchg16b on x86) are allowed, and therefore w
This set of locks will allow us to correctly emulate cmpxchg16
in a parallel TCG. The key observation is that no architecture
supports 16-byte regular atomic load/stores; only "locked" accesses
(e.g. via cmpxchg16b on x86) are allowed, and therefore we can emulate
them by using locks.
We use a sma
